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authorTom Rini <trini@konsulko.com>2019-07-30 19:19:34 -0400
committerTom Rini <trini@konsulko.com>2019-07-30 19:19:34 -0400
commit476a3143d7c1a94b795a4804ab894893f490cf33 (patch)
treed2de199aac021a5d037b22e688ec061748aa5fba /board/xilinx/zynqmp/xil_io.h
parentdcf722ece6aad0c1512a26cdefc2f74a192fa9d2 (diff)
parentcd228cc04afc79c1383be707d0b812f45dfd53aa (diff)
Merge tag 'xilinx-for-v2019.10' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx/FPGA changes for v2019.10 fpga: - Xilinx virtex2 cleanup - Altera cyclon2 cleanup zynq: - Minor Kconfig cleanup - Add psu_init configuration for Z-turn board zynqmp: - Add support for pmufw config passing to PMU - script for psu_init conversion - zcu1275 renaming xilinx: - Add support for UltraZed-EV SoM
Diffstat (limited to 'board/xilinx/zynqmp/xil_io.h')
-rw-r--r--board/xilinx/zynqmp/xil_io.h6
1 files changed, 3 insertions, 3 deletions
diff --git a/board/xilinx/zynqmp/xil_io.h b/board/xilinx/zynqmp/xil_io.h
index c476c902eb..1c1bf32ada 100644
--- a/board/xilinx/zynqmp/xil_io.h
+++ b/board/xilinx/zynqmp/xil_io.h
@@ -9,17 +9,17 @@
#define xil_printf(...)
-void Xil_Out32(unsigned long addr, unsigned long val)
+static void Xil_Out32(unsigned long addr, unsigned long val)
{
writel(val, addr);
}
-int Xil_In32(unsigned long addr)
+static int Xil_In32(unsigned long addr)
{
return readl(addr);
}
-void usleep(u32 sleep)
+static void __maybe_unused usleep(u32 sleep)
{
udelay(sleep);
}