diff options
| author | Michal Simek <michal.simek@xilinx.com> | 2015-07-23 12:03:55 +0200 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2015-07-28 11:56:27 +0200 |
| commit | cb7ea82059069c6509c26b1f705982c6a919a3fe (patch) | |
| tree | 93e4295abe6611457d95008291318581f8da8064 /board/xilinx/zynqmp/zynqmp.c | |
| parent | 6d6e3dbefe1a518bc8fb6a23808770568ff4c125 (diff) | |
ARM: zynqmp: Wire up ethernet controllers
Wire up ethernet controllers and enable MII and BOOTP options.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'board/xilinx/zynqmp/zynqmp.c')
| -rw-r--r-- | board/xilinx/zynqmp/zynqmp.c | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index f5ff64d988..fb43cb0b9a 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -51,6 +51,31 @@ void reset_cpu(ulong addr) { } +int board_eth_init(bd_t *bis) +{ + u32 ret = 0; + +#if defined(CONFIG_ZYNQ_GEM) +# if defined(CONFIG_ZYNQ_GEM0) + ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0, + CONFIG_ZYNQ_GEM_PHY_ADDR0, 0); +# endif +# if defined(CONFIG_ZYNQ_GEM1) + ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR1, + CONFIG_ZYNQ_GEM_PHY_ADDR1, 0); +# endif +# if defined(CONFIG_ZYNQ_GEM2) + ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR2, + CONFIG_ZYNQ_GEM_PHY_ADDR2, 0); +# endif +# if defined(CONFIG_ZYNQ_GEM3) + ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR3, + CONFIG_ZYNQ_GEM_PHY_ADDR3, 0); +# endif +#endif + return ret; +} + #ifdef CONFIG_CMD_MMC int board_mmc_init(bd_t *bd) { |