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authorAaron Williams <awilliams@marvell.com>2020-06-30 12:08:56 +0200
committerDaniel Schwierzeck <daniel.schwierzeck@gmail.com>2020-07-18 15:47:50 +0200
commit0dc4ab9c43ff6a235b4c0c5295a1a9747ea684c9 (patch)
tree27c647c9fbc99170c2761f28d434e8431f668304 /board
parent59aea37abf6bf6d5119a9e2f0237b26bf820b285 (diff)
mips: octeon: Initial minimal support for the Marvell Octeon SoC
This patch adds very basic support for the Octeon III SoCs. Only CFI parallel NOR flash and UART is supported for now. Please note that the basic Octeon port does not include the DDR3/4 initialization yet. This will be added in some follow-up patches later. To still use U-Boot on with this port, the L2 cache (4MiB on Octeon III CN73xx) is used as RAM. This way, U-Boot can boot to the prompt on such boards. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
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