diff options
| author | Jeff Lance <jefflance01@gmail.com> | 2013-01-14 05:32:20 +0000 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2013-02-07 10:36:26 -0500 |
| commit | 13526f7157096dd10ad6027b02af9b1093694170 (patch) | |
| tree | d3a23d1a66369735029c969e363b991454aab864 /board | |
| parent | 3ec36b34fea10c793f6f41859cfcff083d6ee8a3 (diff) | |
Add DDR3 support for AM335x-EVM (Version 1.5A)
AM335x EVM 1.5A uses Micron MT41J512M8RH-125 SDRAM 4Gb (512Mx8) as the
DDR3 chip.
[Hebbar Gururaja <gururaja.hebbar@ti.com>]
- Resolve merge conflict while rebasing. File structure is
changed in the mainline. So re-arrange the code accordingly.
- Update commit message to reflect the DDR3 part number
Signed-off-by: Jeff Lance <j-lance1@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Hebbar Gururaja <gururaja.hebbar@ti.com>
Diffstat (limited to 'board')
| -rw-r--r-- | board/ti/am335x/board.c | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 7332601cbc..b9ac1d5982 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -73,6 +73,12 @@ static inline int board_is_idk(void) return !strncmp(header.config, "SKU#02", 6); } +int board_is_evm_15_or_later(void) +{ + return (!strncmp("A33515BB", header.name, 8) && + strncmp("1.5", header.version, 3) <= 0); +} + /* * Read header information from EEPROM into global structure. */ @@ -197,6 +203,14 @@ static const struct ddr_data ddr3_data = { .datadldiff0 = PHY_DLL_LOCK_DIFF, }; +static const struct ddr_data ddr3_evm_data = { + .datardsratio0 = MT41J512M8RH125_RD_DQS, + .datawdsratio0 = MT41J512M8RH125_WR_DQS, + .datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE, + .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA, + .datadldiff0 = PHY_DLL_LOCK_DIFF, +}; + static const struct cmd_control ddr3_cmd_ctrl_data = { .cmd0csratio = MT41J128MJT125_RATIO, .cmd0dldiff = MT41J128MJT125_DLL_LOCK_DIFF, @@ -211,6 +225,20 @@ static const struct cmd_control ddr3_cmd_ctrl_data = { .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT, }; +static const struct cmd_control ddr3_evm_cmd_ctrl_data = { + .cmd0csratio = MT41J512M8RH125_RATIO, + .cmd0dldiff = MT41J512M8RH125_DLL_LOCK_DIFF, + .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT, + + .cmd1csratio = MT41J512M8RH125_RATIO, + .cmd1dldiff = MT41J512M8RH125_DLL_LOCK_DIFF, + .cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT, + + .cmd2csratio = MT41J512M8RH125_RATIO, + .cmd2dldiff = MT41J512M8RH125_DLL_LOCK_DIFF, + .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT, +}; + static struct emif_regs ddr3_emif_reg_data = { .sdram_config = MT41J128MJT125_EMIF_SDCFG, .ref_ctrl = MT41J128MJT125_EMIF_SDREF, @@ -220,6 +248,16 @@ static struct emif_regs ddr3_emif_reg_data = { .zq_config = MT41J128MJT125_ZQ_CFG, .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY, }; + +static struct emif_regs ddr3_evm_emif_reg_data = { + .sdram_config = MT41J512M8RH125_EMIF_SDCFG, + .ref_ctrl = MT41J512M8RH125_EMIF_SDREF, + .sdram_tim1 = MT41J512M8RH125_EMIF_TIM1, + .sdram_tim2 = MT41J512M8RH125_EMIF_TIM2, + .sdram_tim3 = MT41J512M8RH125_EMIF_TIM3, + .zq_config = MT41J512M8RH125_ZQ_CFG, + .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY, +}; #endif /* @@ -301,6 +339,9 @@ void s_init(void) if (board_is_evm_sk() || board_is_bone_lt()) config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data, &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data); + else if (board_is_evm_15_or_later()) + config_ddr(303, MT41J512M8RH125_IOCTRL_VALUE, &ddr3_evm_data, + &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data); else config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data, &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data); |