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authorWenyou Yang <wenyou.yang@microchip.com>2017-09-13 14:58:50 +0800
committerTom Rini <trini@konsulko.com>2017-09-14 16:02:44 -0400
commit23a19e03589c0b1c4daec082f33a1ecdbf5a4475 (patch)
treeed8e76c277b06a93ea1eb708b6cd7288dc1c6e1b /board
parent2b21cf55cc767bc1303f22c3f6f7b9d6f0845c02 (diff)
board: sama5d2_xplained: Make SPL work on spiflash
Because before switching to a lower clock source, we must switch the clock source first instead of last. So before configuring the PMC_MCKR register, invoke at91_mck_init_down() first. As said in datasheet, the the size of SPL must not exceed the maximum size allowed(64Kbytes). Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'board')
-rw-r--r--board/atmel/sama5d2_xplained/sama5d2_xplained.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/board/atmel/sama5d2_xplained/sama5d2_xplained.c b/board/atmel/sama5d2_xplained/sama5d2_xplained.c
index 7e0cb4228f..5758653030 100644
--- a/board/atmel/sama5d2_xplained/sama5d2_xplained.c
+++ b/board/atmel/sama5d2_xplained/sama5d2_xplained.c
@@ -247,6 +247,16 @@ void at91_pmc_init(void)
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
u32 tmp;
+ /*
+ * while coming from the ROM code, we run on PLLA @ 492 MHz / 164 MHz
+ * so we need to slow down and configure MCKR accordingly.
+ * This is why we have a special flavor of the switching function.
+ */
+ tmp = AT91_PMC_MCKR_PLLADIV_2 |
+ AT91_PMC_MCKR_MDIV_3 |
+ AT91_PMC_MCKR_CSS_MAIN;
+ at91_mck_init_down(tmp);
+
tmp = AT91_PMC_PLLAR_29 |
AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
AT91_PMC_PLLXR_MUL(82) |