Merge branch 'master' of git://www.denx.de/git/u-boot-imx

5 files changed, 134 insertions, 66 deletions

diff --git a/board/dhelectronics/dh_imx6/dh_imx6.c b/board/dhelectronics/dh_imx6/dh_imx6.c
index c76da4d2af..b00d0e4b6d 100644
--- a/board/dhelectronics/dh_imx6/dh_imx6.c
+++ b/board/dhelectronics/dh_imx6/dh_imx6.c
@@ -253,16 +253,10 @@ static void setup_usb(void)
 
 int board_usb_phy_mode(int port)
 {
-	return USB_INIT_HOST;
-}
-
-/* Use only Port 1 == DHCOM USB Host 1 */
-int board_ehci_hcd_init(int port)
-{
 	if (port == 1)
-		return 0;
+		return USB_INIT_HOST;
 	else
-		return -ENODEV;
+		return USB_INIT_DEVICE;
 }
 
 int board_ehci_power(int port, int on)
diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c
index 8afd5da49f..e98aa106ba 100644
--- a/board/freescale/mx6slevk/mx6slevk.c
+++ b/board/freescale/mx6slevk/mx6slevk.c
@@ -27,8 +27,6 @@
 #include <power/pmic.h>
 #include <power/pfuze100_pmic.h>
 #include "../common/pfuze.h"
-#include <usb.h>
-#include <usb/ehci-ci.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -223,49 +221,6 @@ static int setup_fec(void)
 }
 #endif
 
-#ifdef CONFIG_USB_EHCI_MX6
-#define USB_OTHERREGS_OFFSET	0x800
-#define UCTRL_PWR_POL		(1 << 9)
-
-static iomux_v3_cfg_t const usb_otg_pads[] = {
-	/* OTG1 */
-	MX6_PAD_KEY_COL4__USB_USBOTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID | MUX_PAD_CTRL(OTGID_PAD_CTRL),
-	/* OTG2 */
-	MX6_PAD_KEY_COL5__USB_USBOTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
-};
-
-static void setup_usb(void)
-{
-	imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
-					 ARRAY_SIZE(usb_otg_pads));
-}
-
-int board_usb_phy_mode(int port)
-{
-	if (port == 1)
-		return USB_INIT_HOST;
-	else
-		return usb_phy_mode(port);
-}
-
-int board_ehci_hcd_init(int port)
-{
-	u32 *usbnc_usb_ctrl;
-
-	if (port > 1)
-		return -EINVAL;
-
-	usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
-				 port * 4);
-
-	/* Set Power polarity */
-	setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
-
-	return 0;
-}
-#endif
-
 int board_early_init_f(void)
 {
 	setup_iomux_uart();
@@ -287,10 +242,6 @@ int board_init(void)
 	setup_fec();
 #endif
 
-#ifdef CONFIG_USB_EHCI_MX6
-	setup_usb();
-#endif
-
 	return 0;
 }
 
@@ -322,12 +273,15 @@ int board_mmc_getcd(struct mmc *mmc)
 
 	switch (cfg->esdhc_base) {
 	case USDHC1_BASE_ADDR:
+		gpio_request(USDHC1_CD_GPIO, "cd1_gpio");
 		ret = !gpio_get_value(USDHC1_CD_GPIO);
 		break;
 	case USDHC2_BASE_ADDR:
+		gpio_request(USDHC2_CD_GPIO, "cd2_gpio");
 		ret = !gpio_get_value(USDHC2_CD_GPIO);
 		break;
 	case USDHC3_BASE_ADDR:
+		gpio_request(USDHC3_CD_GPIO, "cd3_gpio");
 		ret = !gpio_get_value(USDHC3_CD_GPIO);
 		break;
 	}
diff --git a/board/udoo/udoo.c b/board/udoo/udoo.c
index a359626b81..562f0d863e 100644
--- a/board/udoo/udoo.c
+++ b/board/udoo/udoo.c
@@ -245,8 +245,7 @@ int board_init(void)
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
 #ifdef CONFIG_SATA
-	if (is_cpu_type(MXC_CPU_MX6Q))
-		setup_sata();
+	setup_sata();
 #endif
 	return 0;
 }
diff --git a/board/wandboard/spl.c b/board/wandboard/spl.c
index 00c75d0682..d6f568bb92 100644
--- a/board/wandboard/spl.c
+++ b/board/wandboard/spl.c
@@ -32,6 +32,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define IMX6DQ_DRIVE_STRENGTH		0x30
 #define IMX6SDL_DRIVE_STRENGTH		0x28
+#define IMX6QP_DRIVE_STRENGTH		0x28
 
 /* configure MX6Q/DUAL mmdc DDR io registers */
 static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
@@ -63,6 +64,36 @@ static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
 	.dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
 };
 
+/* configure MX6QP mmdc DDR io registers */
+static struct mx6dq_iomux_ddr_regs mx6qp_ddr_ioregs = {
+	.dram_sdclk_0 = IMX6QP_DRIVE_STRENGTH,
+	.dram_sdclk_1 = IMX6QP_DRIVE_STRENGTH,
+	.dram_cas = IMX6QP_DRIVE_STRENGTH,
+	.dram_ras = IMX6QP_DRIVE_STRENGTH,
+	.dram_reset = IMX6QP_DRIVE_STRENGTH,
+	.dram_sdcke0 = IMX6QP_DRIVE_STRENGTH,
+	.dram_sdcke1 = IMX6QP_DRIVE_STRENGTH,
+	.dram_sdba2 = 0x00000000,
+	.dram_sdodt0 = IMX6QP_DRIVE_STRENGTH,
+	.dram_sdodt1 = IMX6QP_DRIVE_STRENGTH,
+	.dram_sdqs0 = IMX6QP_DRIVE_STRENGTH,
+	.dram_sdqs1 = IMX6QP_DRIVE_STRENGTH,
+	.dram_sdqs2 = IMX6QP_DRIVE_STRENGTH,
+	.dram_sdqs3 = IMX6QP_DRIVE_STRENGTH,
+	.dram_sdqs4 = IMX6QP_DRIVE_STRENGTH,
+	.dram_sdqs5 = IMX6QP_DRIVE_STRENGTH,
+	.dram_sdqs6 = IMX6QP_DRIVE_STRENGTH,
+	.dram_sdqs7 = IMX6QP_DRIVE_STRENGTH,
+	.dram_dqm0 = IMX6QP_DRIVE_STRENGTH,
+	.dram_dqm1 = IMX6QP_DRIVE_STRENGTH,
+	.dram_dqm2 = IMX6QP_DRIVE_STRENGTH,
+	.dram_dqm3 = IMX6QP_DRIVE_STRENGTH,
+	.dram_dqm4 = IMX6QP_DRIVE_STRENGTH,
+	.dram_dqm5 = IMX6QP_DRIVE_STRENGTH,
+	.dram_dqm6 = IMX6QP_DRIVE_STRENGTH,
+	.dram_dqm7 = IMX6QP_DRIVE_STRENGTH,
+};
+
 /* configure MX6Q/DUAL mmdc GRP io registers */
 static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
 	.grp_ddr_type = 0x000c0000,
@@ -81,6 +112,24 @@ static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
 	.grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
 };
 
+/* configure MX6QP mmdc GRP io registers */
+static struct mx6dq_iomux_grp_regs mx6qp_grp_ioregs = {
+	.grp_ddr_type = 0x000c0000,
+	.grp_ddrmode_ctl = 0x00020000,
+	.grp_ddrpke = 0x00000000,
+	.grp_addds = IMX6QP_DRIVE_STRENGTH,
+	.grp_ctlds = IMX6QP_DRIVE_STRENGTH,
+	.grp_ddrmode = 0x00020000,
+	.grp_b0ds = IMX6QP_DRIVE_STRENGTH,
+	.grp_b1ds = IMX6QP_DRIVE_STRENGTH,
+	.grp_b2ds = IMX6QP_DRIVE_STRENGTH,
+	.grp_b3ds = IMX6QP_DRIVE_STRENGTH,
+	.grp_b4ds = IMX6QP_DRIVE_STRENGTH,
+	.grp_b5ds = IMX6QP_DRIVE_STRENGTH,
+	.grp_b6ds = IMX6QP_DRIVE_STRENGTH,
+	.grp_b7ds = IMX6QP_DRIVE_STRENGTH,
+};
+
 /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
 	.dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
@@ -260,15 +309,87 @@ static void ccgr_init(void)
 	writel(0x00C03F3F, &ccm->CCGR0);
 	writel(0x0030FC03, &ccm->CCGR1);
 	writel(0x0FFFC000, &ccm->CCGR2);
-	writel(0x3FF00000, &ccm->CCGR3);
+	writel(0x3FF03000, &ccm->CCGR3);
 	writel(0x00FFF300, &ccm->CCGR4);
 	writel(0x0F0000C3, &ccm->CCGR5);
 	writel(0x000003FF, &ccm->CCGR6);
 }
 
+static void spl_dram_init_imx6qp_lpddr3(void)
+{
+	/* MMDC0_MDSCR set the Configuration request bit during MMDC set up */
+	writel(0x00008000, MMDC_P0_BASE_ADDR + 0x01c);
+	/* Calibrations - ZQ */
+	writel(0xa1390003, MMDC_P0_BASE_ADDR + 0x800);
+	/* write leveling */
+	writel(0x00060004, MMDC_P0_BASE_ADDR + 0x80c);
+	writel(0x000B0004, MMDC_P0_BASE_ADDR + 0x810);
+	writel(0x00000004, MMDC_P1_BASE_ADDR + 0x80c);
+	writel(0x00000000, MMDC_P1_BASE_ADDR + 0x810);
+	/*
+	 * DQS gating, read delay, write delay calibration values
+	 * based on calibration compare of 0x00ffff00
+	 */
+	writel(0x03040314, MMDC_P0_BASE_ADDR + 0x83c);
+	writel(0x03080300, MMDC_P0_BASE_ADDR + 0x840);
+	writel(0x03000310, MMDC_P1_BASE_ADDR + 0x83c);
+	writel(0x0268023C, MMDC_P1_BASE_ADDR + 0x840);
+	writel(0x4034363A, MMDC_P0_BASE_ADDR + 0x848);
+	writel(0x36302C3C, MMDC_P1_BASE_ADDR + 0x848);
+	writel(0x3E3E4046, MMDC_P0_BASE_ADDR + 0x850);
+	writel(0x483A4844, MMDC_P1_BASE_ADDR + 0x850);
+	writel(0x33333333, MMDC_P0_BASE_ADDR + 0x81c);
+	writel(0x33333333, MMDC_P0_BASE_ADDR + 0x820);
+	writel(0x33333333, MMDC_P0_BASE_ADDR + 0x824);
+	writel(0x33333333, MMDC_P0_BASE_ADDR + 0x828);
+	writel(0x33333333, MMDC_P1_BASE_ADDR + 0x81c);
+	writel(0x33333333, MMDC_P1_BASE_ADDR + 0x820);
+	writel(0x33333333, MMDC_P1_BASE_ADDR + 0x824);
+	writel(0x33333333, MMDC_P1_BASE_ADDR + 0x828);
+	writel(0x24912489, MMDC_P0_BASE_ADDR + 0x8c0);
+	writel(0x24914452, MMDC_P1_BASE_ADDR + 0x8c0);
+	writel(0x00000800, MMDC_P0_BASE_ADDR + 0x8b8);
+	writel(0x00000800, MMDC_P1_BASE_ADDR + 0x8b8);
+	/* MMDC init: in DDR3, 64-bit mode, only MMDC0 is initiated */
+	writel(0x00020036, MMDC_P0_BASE_ADDR + 0x004);
+	writel(0x09444040, MMDC_P0_BASE_ADDR + 0x008);
+	writel(0x898E79A4, MMDC_P0_BASE_ADDR + 0x00c);
+	writel(0xDB538F64, MMDC_P0_BASE_ADDR + 0x010);
+	writel(0x01FF00DD, MMDC_P0_BASE_ADDR + 0x014);
+	writel(0x00011740, MMDC_P0_BASE_ADDR + 0x018);
+	writel(0x00008000, MMDC_P0_BASE_ADDR + 0x01c);
+	writel(0x000026D2, MMDC_P0_BASE_ADDR + 0x02c);
+	writel(0x008E1023, MMDC_P0_BASE_ADDR + 0x030);
+	writel(0x00000047, MMDC_P0_BASE_ADDR + 0x040);
+	writel(0x14420000, MMDC_P0_BASE_ADDR + 0x400);
+	writel(0x841A0000, MMDC_P0_BASE_ADDR + 0x000);
+	writel(0x00400c58, MMDC_P0_BASE_ADDR + 0x890);
+	/* add NOC DDR configuration */
+	writel(0x00000000, NOC_DDR_BASE_ADDR + 0x008);
+	writel(0x2871C39B, NOC_DDR_BASE_ADDR + 0x00c);
+	writel(0x000005B4, NOC_DDR_BASE_ADDR + 0x038);
+	writel(0x00000040, NOC_DDR_BASE_ADDR + 0x014);
+	writel(0x00000020, NOC_DDR_BASE_ADDR + 0x028);
+	writel(0x00000020, NOC_DDR_BASE_ADDR + 0x02c);
+	writel(0x02088032, MMDC_P0_BASE_ADDR + 0x01c);
+	writel(0x00008033, MMDC_P0_BASE_ADDR + 0x01c);
+	writel(0x00048031, MMDC_P0_BASE_ADDR + 0x01c);
+	writel(0x19308030, MMDC_P0_BASE_ADDR + 0x01c);
+	writel(0x04008040, MMDC_P0_BASE_ADDR + 0x01c);
+	writel(0x00007800, MMDC_P0_BASE_ADDR + 0x020);
+	writel(0x00022227, MMDC_P0_BASE_ADDR + 0x818);
+	writel(0x00022227, MMDC_P1_BASE_ADDR + 0x818);
+	writel(0x00025576, MMDC_P0_BASE_ADDR + 0x004);
+	writel(0x00011006, MMDC_P0_BASE_ADDR + 0x404);
+	writel(0x00000000, MMDC_P0_BASE_ADDR + 0x01c);
+}
+
 static void spl_dram_init(void)
 {
-	if (is_cpu_type(MXC_CPU_MX6SOLO)) {
+	if (is_mx6dqp()) {
+		mx6dq_dram_iocfg(64, &mx6qp_ddr_ioregs, &mx6qp_grp_ioregs);
+		spl_dram_init_imx6qp_lpddr3();
+	} else if (is_cpu_type(MXC_CPU_MX6SOLO)) {
 		mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
 		mx6_dram_cfg(&mem_s, &mx6s_512m_mmdc_calib, &h5tq2g63dfr);
 	} else if (is_cpu_type(MXC_CPU_MX6DL)) {
diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c
index 6d2609ce11..1e7c11e670 100644
--- a/board/wandboard/wandboard.c
+++ b/board/wandboard/wandboard.c
@@ -435,9 +435,7 @@ int board_early_init_f(void)
 {
 	setup_iomux_uart();
 #ifdef CONFIG_SATA
-	/* Only mx6q wandboard has SATA */
-	if (is_cpu_type(MXC_CPU_MX6Q))
-		setup_sata();
+	setup_sata();
 #endif
 
 	return 0;
@@ -512,7 +510,9 @@ int board_late_init(void)
 #endif
 
 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-	if (is_mx6dq())
+	if (is_mx6dqp())
+		env_set("board_rev", "MX6QP");
+	else if (is_mx6dq())
 		env_set("board_rev", "MX6Q");
 	else
 		env_set("board_rev", "MX6DL");
@@ -534,7 +534,7 @@ int board_init(void)
 
 #if defined(CONFIG_VIDEO_IPUV3)
 	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
-	if (is_mx6dq()) {
+	if (is_mx6dq() || is_mx6dqp()) {
 		setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c2_pad_info);
 		setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c3_pad_info);
 	} else {