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authorFlorin Chiculita <florinlaurentiu.chiculita@nxp.com>2019-04-22 11:57:47 +0300
committerPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>2019-05-22 12:24:24 +0530
commit4dde343d7e9938e781feb3fbe360d6a7befa48f6 (patch)
tree7e10bcbcaef512d7e6778b6d3fc4d3cb8b7286d8 /board
parentd2ebc3823656a66ce0174a0ed3cf217925112a2e (diff)
board: fsl: lx2160ardb: invert AQR107 pins polarity
AQR107 PHYs interrupt pins are active-low, while the GIC expects a level-high signal. Signed-off-by: Florin Chiculita <florinlaurentiu.chiculita@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Diffstat (limited to 'board')
-rw-r--r--board/freescale/lx2160a/lx2160a.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c
index 3875d04543..6109b280c6 100644
--- a/board/freescale/lx2160a/lx2160a.c
+++ b/board/freescale/lx2160a/lx2160a.c
@@ -449,12 +449,20 @@ unsigned long get_board_ddr_clk(void)
int board_init(void)
{
+#if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
+ u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
+#endif
#ifdef CONFIG_ENV_IS_NOWHERE
gd->env_addr = (ulong)&default_environment[0];
#endif
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+#if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
+ /* invert AQR107 IRQ pins polarity */
+ out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR107_IRQ_MASK);
+#endif
+
#ifdef CONFIG_FSL_CAAM
sec_init();
#endif