Merge branch 'master' of git://git.denx.de/u-boot

Signed-off-by: Stefano Babic <sbabic@denx.de>

20 files changed, 176 insertions, 336 deletions

diff --git a/board/Arcturus/ucp1020/cmd_arc.c b/board/Arcturus/ucp1020/cmd_arc.c
index 1c42fee3d6..9579d52ffd 100644
--- a/board/Arcturus/ucp1020/cmd_arc.c
+++ b/board/Arcturus/ucp1020/cmd_arc.c
@@ -15,19 +15,6 @@
 
 #include <asm/io.h>
 
-#ifndef CONFIG_SF_DEFAULT_SPEED
-#   define CONFIG_SF_DEFAULT_SPEED	1000000
-#endif
-#ifndef CONFIG_SF_DEFAULT_MODE
-#   define CONFIG_SF_DEFAULT_MODE	SPI_MODE0
-#endif
-#ifndef CONFIG_SF_DEFAULT_CS
-#   define CONFIG_SF_DEFAULT_CS		0
-#endif
-#ifndef CONFIG_SF_DEFAULT_BUS
-#   define CONFIG_SF_DEFAULT_BUS	0
-#endif
-
 #define MAX_SERIAL_SIZE 15
 #define MAX_HWADDR_SIZE 17
 
diff --git a/board/freescale/ls1021aiot/ls1021aiot.c b/board/freescale/ls1021aiot/ls1021aiot.c
index fb05b55b5c..70992a5ce4 100644
--- a/board/freescale/ls1021aiot/ls1021aiot.c
+++ b/board/freescale/ls1021aiot/ls1021aiot.c
@@ -97,6 +97,8 @@ int dram_init(void)
 	ddrmc_init();
 #endif
 
+	erratum_a008850_post();
+
 	gd->ram_size = DDR_SIZE;
 	return 0;
 }
diff --git a/board/freescale/ls1021aqds/ddr.c b/board/freescale/ls1021aqds/ddr.c
index 98faf9389e..d3e2e53321 100644
--- a/board/freescale/ls1021aqds/ddr.c
+++ b/board/freescale/ls1021aqds/ddr.c
@@ -179,6 +179,8 @@ int fsl_initdram(void)
 	fsl_dp_resume();
 #endif
 
+	erratum_a008850_post();
+
 	gd->ram_size = dram_size;
 
 	return 0;
diff --git a/board/freescale/ls1021aqds/ddr.h b/board/freescale/ls1021aqds/ddr.h
index ff1fe8e2ec..58a8838436 100644
--- a/board/freescale/ls1021aqds/ddr.h
+++ b/board/freescale/ls1021aqds/ddr.h
@@ -5,6 +5,9 @@
 
 #ifndef __DDR_H__
 #define __DDR_H__
+
+void erratum_a008850_post(void);
+
 struct board_specific_parameters {
 	u32 n_ranks;
 	u32 datarate_mhz_high;
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c
index c08be1ee46..2ca2bd9909 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -200,10 +200,6 @@ int board_early_init_f(void)
 #ifdef CONFIG_SPL_BUILD
 void board_init_f(ulong dummy)
 {
-	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
-					CONFIG_SYS_CCI400_OFFSET);
-	unsigned int major;
-
 #ifdef CONFIG_NAND_BOOT
 	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
 	u32 porsr1, pinctl;
@@ -240,10 +236,6 @@ void board_init_f(ulong dummy)
 	i2c_init_all();
 #endif
 
-	major = get_soc_major_rev();
-	if (major == SOC_MAJOR_VER_1_0)
-		out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
-
 	timer_init();
 	dram_init();
 
@@ -420,22 +412,12 @@ int misc_init_r(void)
 
 int board_init(void)
 {
-	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
-					CONFIG_SYS_CCI400_OFFSET);
-	unsigned int major;
-
 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
 	erratum_a010315();
 #endif
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
 	erratum_a009942_check_cpo();
 #endif
-	major = get_soc_major_rev();
-	if (major == SOC_MAJOR_VER_1_0) {
-		/* Set CCI-400 control override register to
-		 * enable barrier transaction */
-		out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
-	}
 
 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 
@@ -456,18 +438,6 @@ int board_init(void)
 #if defined(CONFIG_DEEP_SLEEP)
 void board_sleep_prepare(void)
 {
-	struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
-						CONFIG_SYS_CCI400_OFFSET);
-	unsigned int major;
-
-	major = get_soc_major_rev();
-	if (major == SOC_MAJOR_VER_1_0) {
-		/* Set CCI-400 control override register to
-		 * enable barrier transaction */
-		out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
-	}
-
-
 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
 	enable_layerscape_ns_access();
 #endif
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c
index beb82cebb6..01ba1bc962 100644
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -222,6 +222,8 @@ int dram_init(void)
 	ddrmc_init();
 #endif
 
+	erratum_a008850_post();
+
 	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
 
 #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
diff --git a/board/freescale/lx2160a/eth_lx2160aqds.c b/board/freescale/lx2160a/eth_lx2160aqds.c
index 1e98d0c1f9..f6e22d7337 100644
--- a/board/freescale/lx2160a/eth_lx2160aqds.c
+++ b/board/freescale/lx2160a/eth_lx2160aqds.c
@@ -628,8 +628,9 @@ int fdt_fixup_dpmac_phy_handle(void *fdt, int dpmac_id, int node_phandle)
 int fdt_get_ioslot_offset(void *fdt, struct mii_dev *mii_dev, int fpga_offset)
 {
 	char mdio_ioslot_str[] = "mdio@00";
-	char mdio_mux_str[] = "mdio-mux-0";
 	struct lx2160a_qds_mdio *priv;
+	u64 reg;
+	u32 phandle;
 	int offset, mux_val;
 
 	/*Test if the MDIO bus is real mdio bus or muxing front end ?*/
@@ -643,15 +644,32 @@ int fdt_get_ioslot_offset(void *fdt, struct mii_dev *mii_dev, int fpga_offset)
 	debug("real_bus_num = %d, ioslot = %d\n",
 	      priv->realbusnum, priv->ioslot);
 
-	sprintf(mdio_mux_str, "mdio-mux-%1d", priv->realbusnum);
-	offset = fdt_subnode_offset(fdt, fpga_offset, mdio_mux_str);
+	if (priv->realbusnum == EMI1)
+		reg = CONFIG_SYS_FSL_WRIOP1_MDIO1;
+	else
+		reg = CONFIG_SYS_FSL_WRIOP1_MDIO2;
+
+	offset = fdt_node_offset_by_compat_reg(fdt, "fsl,fman-memac-mdio", reg);
+	if (offset < 0) {
+		printf("mdio@%llx node not found in device tree\n", reg);
+		return offset;
+	}
+
+	phandle = fdt_get_phandle(fdt, offset);
+	phandle = cpu_to_fdt32(phandle);
+	offset = fdt_node_offset_by_prop_value(fdt, -1, "mdio-parent-bus",
+					       &phandle, 4);
 	if (offset < 0) {
-		printf("%s node not found under node %s in device tree\n",
-		       mdio_mux_str, fdt_get_name(fdt, fpga_offset, NULL));
+		printf("mdio-mux-%d node not found in device tree\n",
+		       priv->realbusnum == EMI1 ? 1 : 2);
 		return offset;
 	}
 
 	mux_val = lx2160a_qds_get_mdio_mux_val(priv->realbusnum, priv->ioslot);
+	if (priv->realbusnum == EMI1)
+		mux_val >>= BRDCFG4_EMI1SEL_SHIFT;
+	else
+		mux_val >>= BRDCFG4_EMI2SEL_SHIFT;
 	sprintf(mdio_ioslot_str, "mdio@%x", (u8)mux_val);
 
 	offset = fdt_subnode_offset(fdt, offset, mdio_ioslot_str);
@@ -675,7 +693,9 @@ int fdt_create_phy_node(void *fdt, int offset, u8 phyaddr, int *subnodeoffset,
 
 	*subnodeoffset = fdt_add_subnode(fdt, offset, phy_node_name);
 	if (*subnodeoffset <= 0) {
-		printf("Could not add subnode %s\n", phy_node_name);
+		printf("Could not add subnode %s inside node %s err = %s\n",
+		       phy_node_name, fdt_get_name(fdt, offset, NULL),
+		       fdt_strerror(*subnodeoffset));
 		return *subnodeoffset;
 	}
 
@@ -779,7 +799,6 @@ int fdt_fixup_board_phy(void *fdt)
 			}
 			if (dpmac_id == NUM_WRIOP_PORTS)
 				continue;
-
 			ret = fdt_create_phy_node(fdt, offset, i,
 						  &subnodeoffset,
 						  phy_dev, phandle);
@@ -792,6 +811,11 @@ int fdt_fixup_board_phy(void *fdt)
 				fdt_del_node(fdt, subnodeoffset);
 				break;
 			}
+			/* calculate offset again as new node addition may have
+			 * changed offset;
+			 */
+			offset = fdt_get_ioslot_offset(fdt, mii_dev,
+						       fpga_offset);
 			phandle++;
 		}
 
diff --git a/board/raspberrypi/rpi/MAINTAINERS b/board/raspberrypi/rpi/MAINTAINERS
index cce1a7ad76..4f1b23efc8 100644
--- a/board/raspberrypi/rpi/MAINTAINERS
+++ b/board/raspberrypi/rpi/MAINTAINERS
@@ -1,5 +1,5 @@
 RPI BOARD
-M:	Alexander Graf <agraf@suse.de>
+M:	Matthias Brugger <mbrugger@suse.com>
 S:	Maintained
 F:	board/raspberrypi/rpi/
 F:	include/configs/rpi.h
diff --git a/board/samsung/arndale/MAINTAINERS b/board/samsung/arndale/MAINTAINERS
index 7dc17854d1..aa64c7a187 100644
--- a/board/samsung/arndale/MAINTAINERS
+++ b/board/samsung/arndale/MAINTAINERS
@@ -1,5 +1,5 @@
 ARNDALE BOARD
-M:	Chander Kashyap <k.chander@samsung.com>
+M:	Krzysztof Kozlowski <krzk@kernel.org>
 S:	Maintained
 F:	board/samsung/arndale/
 F:	include/configs/arndale.h
diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c
index 96228a86a1..9adbd1e2cf 100644
--- a/board/samsung/common/board.c
+++ b/board/samsung/common/board.c
@@ -249,11 +249,22 @@ int board_eth_init(bd_t *bis)
 	return 0;
 }
 
-#ifdef CONFIG_DISPLAY_BOARDINFO
+#if defined(CONFIG_DISPLAY_BOARDINFO) || defined(CONFIG_DISPLAY_BOARDINFO_LATE)
 int checkboard(void)
 {
 	if (IS_ENABLED(CONFIG_BOARD_TYPES)) {
-		const char *board_info = get_board_type();
+		const char *board_info;
+
+		if (IS_ENABLED(CONFIG_DISPLAY_BOARDINFO_LATE)) {
+			/*
+			 * Printing type requires having revision, although
+			 * this will succeed only if done late.
+			 * Otherwise revision will be set in misc_init_r().
+			 */
+			set_board_revision();
+		}
+
+		board_info = get_board_type();
 
 		if (board_info)
 			printf("Type:  %s\n", board_info);
@@ -287,6 +298,16 @@ int board_late_init(void)
 #ifdef CONFIG_MISC_INIT_R
 int misc_init_r(void)
 {
+	if (IS_ENABLED(CONFIG_BOARD_TYPES) &&
+	    !IS_ENABLED(CONFIG_DISPLAY_BOARDINFO_LATE)) {
+		/*
+		 * If revision was not set by late display boardinfo,
+		 * set it here. At this point regulators should be already
+		 * available.
+		 */
+		set_board_revision();
+	}
+
 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 	set_board_info();
 #endif
diff --git a/board/samsung/common/bootscripts/autoboot.cmd b/board/samsung/common/bootscripts/autoboot.cmd
index 11c724c4e0..d66bcccf5d 100644
--- a/board/samsung/common/bootscripts/autoboot.cmd
+++ b/board/samsung/common/bootscripts/autoboot.cmd
@@ -3,7 +3,7 @@
 # ./tools/mkimage -c none -A arm -T script -d autoboot.cmd boot.scr
 #
 # It requires a list of environment variables to be defined before load:
-# platform dependent: boardname, fdtfile, console
+# platform dependent: board_name, fdtfile, console
 # system dependent: mmcbootdev, mmcbootpart, mmcrootdev, mmcrootpart, rootfstype
 #
 setenv fdtaddr     "40800000"
@@ -35,17 +35,17 @@ else
 	setenv initrd_addr -;
 fi;"
 
-#### Routine: boot_fit - check that env $boardname is set and boot proper config of ITB image
+#### Routine: boot_fit - check that env $board_name is set and boot proper config of ITB image
 setenv setboot_fit "
-if test -e '${boardname}'; then
+if test -e '${board_name}'; then
 	setenv fdt_addr ;
 	setenv initrd_addr ;
 	setenv kerneladdr  0x42000000;
 	setenv kernelname  Image.itb;
-	setenv itbcfg      "\"#${boardname}\"";
+	setenv itbcfg      "\"#${board_name}\"";
 	setenv imgbootcmd  bootm;
 else
-	echo Warning! Variable: \$boardname is undefined!;
+	echo Warning! Variable: \$board_name is undefined!;
 fi"
 
 #### Routine: setboot_uimg - prepare env to boot uImage
diff --git a/board/samsung/common/exynos5-dt-types.c b/board/samsung/common/exynos5-dt-types.c
index 7a86e91877..516c32923e 100644
--- a/board/samsung/common/exynos5-dt-types.c
+++ b/board/samsung/common/exynos5-dt-types.c
@@ -57,12 +57,48 @@ static unsigned int odroid_get_rev(void)
 	return 0;
 }
 
+/*
+ * Read ADC at least twice and check the resuls.  If regulator providing voltage
+ * on to measured point was just turned on, first reads might require time
+ * to stabilize.
+ */
+static int odroid_get_adc_val(unsigned int *adcval)
+{
+	unsigned int adcval_prev = 0;
+	int ret, retries = 20;
+
+	ret = adc_channel_single_shot("adc", CONFIG_ODROID_REV_AIN,
+				      &adcval_prev);
+	if (ret)
+		return ret;
+
+	while (retries--) {
+		mdelay(5);
+
+		ret = adc_channel_single_shot("adc", CONFIG_ODROID_REV_AIN,
+					      adcval);
+		if (ret)
+			return ret;
+
+		/*
+		 * If difference between ADC reads is less than 3%,
+		 * accept the result
+		 */
+		if ((100 * abs(*adcval - adcval_prev) / adcval_prev) < 3)
+			return ret;
+
+		adcval_prev = *adcval;
+	}
+
+	return ret;
+}
+
 static int odroid_get_board_type(void)
 {
 	unsigned int adcval;
 	int ret, i;
 
-	ret = adc_channel_single_shot("adc", CONFIG_ODROID_REV_AIN, &adcval);
+	ret = odroid_get_adc_val(&adcval);
 	if (ret)
 		goto rev_default;
 
@@ -192,8 +228,11 @@ const char *get_board_type(void)
 
 /**
  * set_board_type() - set board type in gd->board_type.
- * As default type set EXYNOS5_BOARD_GENERIC, if detect Odroid,
- * then set its proper type.
+ * As default type set EXYNOS5_BOARD_GENERIC. If Odroid is detected,
+ * set its proper type based on device tree.
+ *
+ * This might be called early when some more specific ways to detect revision
+ * are not yet available.
  */
 void set_board_type(void)
 {
@@ -211,8 +250,15 @@ void set_board_type(void)
 		gd->board_type = of_match->data;
 		break;
 	}
+}
 
-	/* If Odroid, then check its revision */
+/**
+ * set_board_revision() - set detailed board type in gd->board_type.
+ * Should be called when resources (e.g. regulators) are available
+ * so ADC can be used to detect the specific revision of a board.
+ */
+void set_board_revision(void)
+{
 	if (board_is_odroidxu3())
 		gd->board_type = odroid_get_board_type();
 }
diff --git a/board/samsung/common/misc.c b/board/samsung/common/misc.c
index 05243fc896..53cd1b2907 100644
--- a/board/samsung/common/misc.c
+++ b/board/samsung/common/misc.c
@@ -101,7 +101,7 @@ void set_board_info(void)
 		bdtype = "";
 
 	sprintf(info, "%s%s", bdname, bdtype);
-	env_set("boardname", info);
+	env_set("board_name", info);
 #endif
 	snprintf(info, ARRAY_SIZE(info),  "%s%x-%s%s.dtb",
 		 CONFIG_SYS_SOC, s5p_cpu_id, bdname, bdtype);
diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c
index 552333fe86..3e594fd850 100644
--- a/board/samsung/odroid/odroid.c
+++ b/board/samsung/odroid/odroid.c
@@ -54,6 +54,14 @@ void set_board_type(void)
 		gd->board_type = ODROID_TYPE_U3;
 }
 
+void set_board_revision(void)
+{
+	/*
+	 * Revision already set by set_board_type() because it can be
+	 * executed early.
+	 */
+}
+
 const char *get_board_type(void)
 {
 	const char *board_type[] = {"u3", "x2"};
@@ -462,18 +470,33 @@ struct dwc2_plat_otg_data s5pc210_otg_data = {
 
 #if defined(CONFIG_USB_GADGET) || defined(CONFIG_CMD_USB)
 
+static void set_usb3503_ref_clk(void)
+{
+#ifdef CONFIG_BOARD_TYPES
+	/*
+	 * gpx3-0 chooses primary (low) or secondary (high) reference clock
+	 * frequencies table.  The choice of clock is done through hard-wired
+	 * REF_SEL pins.
+	 * The Odroid Us have reference clock at 24 MHz (00 entry from secondary
+	 * table) and Odroid Xs have it at 26 MHz (01 entry from primary table).
+	 */
+	if (gd->board_type == ODROID_TYPE_U3)
+		gpio_direction_output(EXYNOS4X12_GPIO_X30, 0);
+	else
+		gpio_direction_output(EXYNOS4X12_GPIO_X30, 1);
+#else
+	/* Choose Odroid Xs frequency without board types */
+	gpio_direction_output(EXYNOS4X12_GPIO_X30, 1);
+#endif /* CONFIG_BOARD_TYPES */
+}
+
 int board_usb_init(int index, enum usb_init_type init)
 {
 #ifdef CONFIG_CMD_USB
 	struct udevice *dev;
 	int ret;
 
-	/* Set Ref freq 0 => 24MHz, 1 => 26MHz*/
-	/* Odroid Us have it at 24MHz, Odroid Xs at 26MHz */
-	if (gd->board_type == ODROID_TYPE_U3)
-		gpio_direction_output(EXYNOS4X12_GPIO_X30, 0);
-	else
-		gpio_direction_output(EXYNOS4X12_GPIO_X30, 1);
+	set_usb3503_ref_clk();
 
 	/* Disconnect, Reset, Connect */
 	gpio_direction_output(EXYNOS4X12_GPIO_X34, 0);
diff --git a/board/synopsys/axs10x/Makefile b/board/synopsys/axs10x/Makefile
index 340e12c443..dd5ee680e7 100644
--- a/board/synopsys/axs10x/Makefile
+++ b/board/synopsys/axs10x/Makefile
@@ -3,4 +3,3 @@
 # Copyright (C) 2013-2016 Synopsys, Inc. All rights reserved.
 
 obj-y	+= axs10x.o
-obj-$(CONFIG_CMD_NAND) += nand.o
diff --git a/board/synopsys/axs10x/nand.c b/board/synopsys/axs10x/nand.c
deleted file mode 100644
index 8108460f58..0000000000
--- a/board/synopsys/axs10x/nand.c
+++ /dev/null
@@ -1,242 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
- */
-
-#include <bouncebuf.h>
-#include <common.h>
-#include <malloc.h>
-#include <nand.h>
-#include <asm/io.h>
-#include "axs10x.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define BUS_WIDTH	8		/* AXI data bus width in bytes	*/
-
-/* DMA buffer descriptor bits & masks */
-#define BD_STAT_OWN			(1 << 31)
-#define BD_STAT_BD_FIRST		(1 << 3)
-#define BD_STAT_BD_LAST			(1 << 2)
-#define BD_SIZES_BUFFER1_MASK		0xfff
-
-#define BD_STAT_BD_COMPLETE	(BD_STAT_BD_FIRST | BD_STAT_BD_LAST)
-
-/* Controller command flags */
-#define B_WFR		(1 << 19)	/* 1b - Wait for ready		*/
-#define B_LC		(1 << 18)	/* 1b - Last cycle		*/
-#define B_IWC		(1 << 13)	/* 1b - Interrupt when complete	*/
-
-/* NAND cycle types */
-#define B_CT_ADDRESS	(0x0 << 16)	/* Address operation		*/
-#define B_CT_COMMAND	(0x1 << 16)	/* Command operation		*/
-#define B_CT_WRITE	(0x2 << 16)	/* Write operation		*/
-#define B_CT_READ	(0x3 << 16)	/* Write operation		*/
-
-enum nand_isr_t {
-	NAND_ISR_DATAREQUIRED = 0,
-	NAND_ISR_TXUNDERFLOW,
-	NAND_ISR_TXOVERFLOW,
-	NAND_ISR_DATAAVAILABLE,
-	NAND_ISR_RXUNDERFLOW,
-	NAND_ISR_RXOVERFLOW,
-	NAND_ISR_TXDMACOMPLETE,
-	NAND_ISR_RXDMACOMPLETE,
-	NAND_ISR_DESCRIPTORUNAVAILABLE,
-	NAND_ISR_CMDDONE,
-	NAND_ISR_CMDAVAILABLE,
-	NAND_ISR_CMDERROR,
-	NAND_ISR_DATATRANSFEROVER,
-	NAND_ISR_NONE
-};
-
-enum nand_regs_t {
-	AC_FIFO = 0,		/* address and command fifo */
-	IDMAC_BDADDR = 0x18,	/* idmac descriptor list base address */
-	INT_STATUS = 0x118,	/* interrupt status register */
-	INT_CLR_STATUS = 0x120,	/* interrupt clear status register */
-};
-
-struct nand_bd {
-	uint32_t status;	/* DES0 */
-	uint32_t sizes;		/* DES1 */
-	uint32_t buffer_ptr0;	/* DES2 */
-	uint32_t buffer_ptr1;	/* DES3 */
-};
-
-#define NAND_REG_WRITE(r, v)	\
-	writel(v, (volatile void __iomem *)(CONFIG_SYS_NAND_BASE + r))
-#define NAND_REG_READ(r)		\
-	readl((const volatile void __iomem *)(CONFIG_SYS_NAND_BASE + r))
-
-static struct nand_bd *bd;	/* DMA buffer descriptors	*/
-
-/**
- * axs101_nand_write_buf -  write buffer to chip
- * @mtd:	MTD device structure
- * @buf:	data buffer
- * @len:	number of bytes to write
- */
-static uint32_t nand_flag_is_set(uint32_t flag)
-{
-	uint32_t reg = NAND_REG_READ(INT_STATUS);
-
-	if (reg & (1 << NAND_ISR_CMDERROR))
-		return 0;
-
-	if (reg & (1 << flag)) {
-		NAND_REG_WRITE(INT_CLR_STATUS, 1 << flag);
-		return 1;
-	}
-
-	return 0;
-}
-
-/**
- * axs101_nand_write_buf -  write buffer to chip
- * @mtd:	MTD device structure
- * @buf:	data buffer
- * @len:	number of bytes to write
- */
-static void axs101_nand_write_buf(struct mtd_info *mtd, const u_char *buf,
-				   int len)
-{
-	struct bounce_buffer bbstate;
-
-	bounce_buffer_start(&bbstate, (void *)buf, len, GEN_BB_READ);
-
-	/* Setup buffer descriptor */
-	writel(BD_STAT_OWN | BD_STAT_BD_COMPLETE, &bd->status);
-	writel(ALIGN(len, BUS_WIDTH) & BD_SIZES_BUFFER1_MASK, &bd->sizes);
-	writel(bbstate.bounce_buffer, &bd->buffer_ptr0);
-	writel(0, &bd->buffer_ptr1);
-
-	/* Flush modified buffer descriptor */
-	flush_dcache_range((unsigned long)bd,
-			   (unsigned long)bd + sizeof(struct nand_bd));
-
-	/* Issue "write" command */
-	NAND_REG_WRITE(AC_FIFO, B_CT_WRITE | B_WFR | B_IWC | B_LC | (len-1));
-
-	/* Wait for NAND command and DMA to complete */
-	while (!nand_flag_is_set(NAND_ISR_CMDDONE))
-		;
-	while (!nand_flag_is_set(NAND_ISR_TXDMACOMPLETE))
-		;
-
-	bounce_buffer_stop(&bbstate);
-}
-
-/**
- * axs101_nand_read_buf -  read chip data into buffer
- * @mtd:	MTD device structure
- * @buf:	buffer to store data
- * @len:	number of bytes to read
- */
-static void axs101_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
-{
-	struct bounce_buffer bbstate;
-
-	bounce_buffer_start(&bbstate, buf, len, GEN_BB_WRITE);
-
-	/* Setup buffer descriptor */
-	writel(BD_STAT_OWN | BD_STAT_BD_COMPLETE, &bd->status);
-	writel(ALIGN(len, BUS_WIDTH) & BD_SIZES_BUFFER1_MASK, &bd->sizes);
-	writel(bbstate.bounce_buffer, &bd->buffer_ptr0);
-	writel(0, &bd->buffer_ptr1);
-
-	/* Flush modified buffer descriptor */
-	flush_dcache_range((unsigned long)bd,
-			   (unsigned long)bd + sizeof(struct nand_bd));
-
-	/* Issue "read" command */
-	NAND_REG_WRITE(AC_FIFO, B_CT_READ | B_WFR | B_IWC | B_LC | (len - 1));
-
-	/* Wait for NAND command and DMA to complete */
-	while (!nand_flag_is_set(NAND_ISR_CMDDONE))
-		;
-	while (!nand_flag_is_set(NAND_ISR_RXDMACOMPLETE))
-		;
-
-	bounce_buffer_stop(&bbstate);
-}
-
-/**
- * axs101_nand_read_byte -  read one byte from the chip
- * @mtd:	MTD device structure
- */
-static u_char axs101_nand_read_byte(struct mtd_info *mtd)
-{
-	u8 byte;
-
-	axs101_nand_read_buf(mtd, (uchar *)&byte, sizeof(byte));
-	return byte;
-}
-
-/**
- * axs101_nand_read_word -  read one word from the chip
- * @mtd:	MTD device structure
- */
-static u16 axs101_nand_read_word(struct mtd_info *mtd)
-{
-	u16 word;
-
-	axs101_nand_read_buf(mtd, (uchar *)&word, sizeof(word));
-	return word;
-}
-
-/**
- * axs101_nand_hwcontrol - NAND control functions wrapper.
- * @mtd:	MTD device structure
- * @cmd:	Command
- */
-static void axs101_nand_hwcontrol(struct mtd_info *mtdinfo, int cmd,
-				   unsigned int ctrl)
-{
-	if (cmd == NAND_CMD_NONE)
-		return;
-
-	cmd = cmd & 0xff;
-
-	switch (ctrl & (NAND_ALE | NAND_CLE)) {
-	/* Address */
-	case NAND_ALE:
-		cmd |= B_CT_ADDRESS;
-		break;
-
-	/* Command */
-	case NAND_CLE:
-		cmd |= B_CT_COMMAND | B_WFR;
-
-		break;
-
-	default:
-		debug("%s: unknown ctrl %#x\n", __func__, ctrl);
-	}
-
-	NAND_REG_WRITE(AC_FIFO, cmd | B_LC);
-	while (!nand_flag_is_set(NAND_ISR_CMDDONE))
-		;
-}
-
-int board_nand_init(struct nand_chip *nand)
-{
-	bd = (struct nand_bd *)memalign(ARCH_DMA_MINALIGN,
-					sizeof(struct nand_bd));
-
-	/* Set buffer descriptor address in IDMAC */
-	NAND_REG_WRITE(IDMAC_BDADDR, bd);
-
-	nand->ecc.mode = NAND_ECC_SOFT;
-	nand->cmd_ctrl = axs101_nand_hwcontrol;
-	nand->read_byte = axs101_nand_read_byte;
-	nand->read_word = axs101_nand_read_word;
-	nand->write_buf = axs101_nand_write_buf;
-	nand->read_buf = axs101_nand_read_buf;
-
-	/* MBv3 has NAND IC with 16-bit data bus */
-	if (gd->board_type == AXS_MB_V3)
-		nand->options |= NAND_BUSWIDTH_16;
-
-	return 0;
-}
diff --git a/board/synopsys/hsdk/README b/board/synopsys/hsdk/README
index e29a6a1727..9155f17c6e 100644
--- a/board/synopsys/hsdk/README
+++ b/board/synopsys/hsdk/README
@@ -83,10 +83,11 @@ Useful notes on bulding and using of U-Boot on ARC HS Development Kit (AKA HSDK)
       HSDK board.
 
       Note that Python3 script is used for generation of a header, thus
-      to get that done it's required to have Python3 with elftools installed.
-      On CentOS/RHEL/Fedora this could be installed with:
+      to get that done it's required to have Python3 with "pyelftools" installed.
+
+      "pyelftools" could be installed with help of "pip" even w/o root rights:
       ------------------------->8----------------------
-      sudo dnf install python3-pyelftools
+      python3 -m pip install --user pyelftools
       ------------------------->8----------------------
 
    EXECUTING U-BOOT
diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c
index 7063345dcc..1a903f13a6 100644
--- a/board/ti/am57xx/board.c
+++ b/board/ti/am57xx/board.c
@@ -1096,6 +1096,16 @@ int board_fit_config_name_match(const char *name)
 }
 #endif
 
+#if CONFIG_IS_ENABLED(FASTBOOT) && !CONFIG_IS_ENABLED(ENV_IS_NOWHERE)
+int fastboot_set_reboot_flag(void)
+{
+	printf("Setting reboot to fastboot flag ...\n");
+	env_set("dofastboot", "1");
+	env_save();
+	return 0;
+}
+#endif
+
 #ifdef CONFIG_TI_SECURE_DEVICE
 void board_fit_image_post_process(void **p_image, size_t *p_size)
 {
@@ -1107,15 +1117,5 @@ void board_tee_image_process(ulong tee_image, size_t tee_size)
 	secure_tee_install((u32)tee_image);
 }
 
-#if CONFIG_IS_ENABLED(FASTBOOT) && !CONFIG_IS_ENABLED(ENV_IS_NOWHERE)
-int fastboot_set_reboot_flag(void)
-{
-	printf("Setting reboot to fastboot flag ...\n");
-	env_set("dofastboot", "1");
-	env_save();
-	return 0;
-}
-#endif
-
 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
 #endif
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index d69641e3a0..060c471032 100644
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@@ -1092,6 +1092,16 @@ int board_fit_config_name_match(const char *name)
 }
 #endif
 
+#if CONFIG_IS_ENABLED(FASTBOOT) && !CONFIG_IS_ENABLED(ENV_IS_NOWHERE)
+int fastboot_set_reboot_flag(void)
+{
+	printf("Setting reboot to fastboot flag ...\n");
+	env_set("dofastboot", "1");
+	env_save();
+	return 0;
+}
+#endif
+
 #ifdef CONFIG_TI_SECURE_DEVICE
 void board_fit_image_post_process(void **p_image, size_t *p_size)
 {
@@ -1103,15 +1113,5 @@ void board_tee_image_process(ulong tee_image, size_t tee_size)
 	secure_tee_install((u32)tee_image);
 }
 
-#if CONFIG_IS_ENABLED(FASTBOOT) && !CONFIG_IS_ENABLED(ENV_IS_NOWHERE)
-int fastboot_set_reboot_flag(void)
-{
-	printf("Setting reboot to fastboot flag ...\n");
-	env_set("dofastboot", "1");
-	env_save();
-	return 0;
-}
-#endif
-
 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
 #endif
diff --git a/board/tqc/tqma6/tqma6.c b/board/tqc/tqma6/tqma6.c
index 816672edc6..372a17cd51 100644
--- a/board/tqc/tqma6/tqma6.c
+++ b/board/tqc/tqma6/tqma6.c
@@ -155,11 +155,13 @@ __weak void tqma6_iomuxc_spi(void)
 					 ARRAY_SIZE(tqma6_ecspi1_pads));
 }
 
+#if defined(CONFIG_SF_DEFAULT_BUS) && defined(CONFIG_SF_DEFAULT_CS)
 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 {
 	return ((bus == CONFIG_SF_DEFAULT_BUS) &&
 		(cs == CONFIG_SF_DEFAULT_CS)) ? TQMA6_SF_CS_GPIO : -1;
 }
+#endif
 
 static struct i2c_pads_info tqma6_i2c3_pads = {
 	/* I2C3: on board LM75, M24C64,  */