diff options
| author | Yuan Yao <yao.yuan@nxp.com> | 2016-06-08 18:24:52 +0800 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-06-10 13:44:59 -0700 |
| commit | 916d9f099edcb2a020ec3f291f0fa0e6fab0f9a5 (patch) | |
| tree | 50c75266d4b9979bd7e6fbcbf1db64614fa505af /board | |
| parent | 9d10c2d3fe6852501a4c43853fe3d2469903a2bb (diff) | |
armv8: ls2080aqds: Select QSPI CLK div via SCFG
QSPI module output SCLK divisor value is configured through SCFG.
Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'board')
| -rw-r--r-- | board/freescale/ls2080aqds/ls2080aqds.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c index 897793d85b..b60206b4e4 100644 --- a/board/freescale/ls2080aqds/ls2080aqds.c +++ b/board/freescale/ls2080aqds/ls2080aqds.c @@ -26,6 +26,7 @@ #define PIN_MUX_SEL_SDHC 0x00 #define PIN_MUX_SEL_DSPI 0x0a +#define SCFG_QSPICLKCTRL_DIV_20 (5 << 27) #define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) | value) @@ -219,6 +220,10 @@ int board_init(void) int board_early_init_f(void) { fsl_lsch3_early_init_f(); +#ifdef CONFIG_FSL_QSPI + /* input clk: 1/2 platform clk, output: input/20 */ + out_le32(SCFG_BASE + SCFG_QSPICLKCTLR, SCFG_QSPICLKCTRL_DIV_20); +#endif return 0; } |