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authorPaul Gortmaker <paul.gortmaker@windriver.com>2009-09-18 19:08:41 -0400
committerKumar Gala <galak@kernel.crashing.org>2009-09-24 12:05:00 -0500
commit9b3ba24f18900633a394416cc056c44a1a6eb754 (patch)
treef58e3b0801f00356509af60e415df9a000411329 /board
parentded58f4153923dfff16d2f96495bd7acf1f7e10e (diff)
sbc8548: enable access to second bank of flash
The sbc8548 has a 64MB SODIMM flash module off of CS6 that previously wasn't enumerated by u-boot. There were already BR6/OR6 settings for it [used by cpu_init_f()] but there was no TLB entry and it wasn't in the list of flash banks reported to u-boot. The location of the 64MB flash is "pulled back" 8MB from a 64MB boundary, in order to allow address space for the 8MB boot flash that is at the end of 32 bit address space. This means creating two 4MB TLB entries for the 8MB chunk, and then expanding the original boot flash entry to 64MB in order to cover the 8MB boot flash and the remainder (56MB) of the user flash. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'board')
-rw-r--r--board/sbc8548/tlb.c28
1 files changed, 24 insertions, 4 deletions
diff --git a/board/sbc8548/tlb.c b/board/sbc8548/tlb.c
index ddcb532eef..a0b4e36e7b 100644
--- a/board/sbc8548/tlb.c
+++ b/board/sbc8548/tlb.c
@@ -45,13 +45,15 @@ struct fsl_e_tlb_entry tlb_table[] = {
0, 0, BOOKE_PAGESZ_4K, 0),
/*
- * TLB 0: 16M Non-cacheable, guarded
- * 0xff800000 16M TLB for 8MB FLASH
+ * TLB 0: 64M Non-cacheable, guarded
+ * 0xfc000000 56M 8MB -> 64MB of user flash
+ * 0xff800000 8M boot FLASH
* Out of reset this entry is only 4K.
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
+ SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x800000,
+ CONFIG_SYS_ALT_FLASH + 0x800000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_16M, 1),
+ 0, 0, BOOKE_PAGESZ_64M, 1),
/*
* TLB 1: 256M Non-cacheable, guarded
@@ -107,6 +109,24 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY(1, CONFIG_SYS_EPLD_BASE, CONFIG_SYS_EPLD_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 6, BOOKE_PAGESZ_16M, 1),
+
+ /*
+ * TLB 7: 4M Non-cacheable, guarded
+ * 0xfb800000 4M 1st 4MB block of 64MB user FLASH
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 7, BOOKE_PAGESZ_4M, 1),
+
+ /*
+ * TLB 8: 4M Non-cacheable, guarded
+ * 0xfbc00000 4M 2nd 4MB block of 64MB user FLASH
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x400000,
+ CONFIG_SYS_ALT_FLASH + 0x400000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 8, BOOKE_PAGESZ_4M, 1),
+
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);