Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'

19 files changed, 568 insertions, 54 deletions

diff --git a/board/cm_t35/Makefile b/board/compulab/cm_t35/Makefile
index bde56e61f4..31d9bbbfe3 100644
--- a/board/cm_t35/Makefile
+++ b/board/compulab/cm_t35/Makefile
@@ -1,6 +1,8 @@
 #
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# (C) Copyright 2011 - 2013 CompuLab, Ltd. <www.compulab.co.il>
+#
+# Authors: Nikita Kiryanov <nikita@compulab.co.il>
+#	   Igor Grinberg <grinberg@compulab.co.il>
 #
 # See file CREDITS for list of people who contributed to this
 # project.
@@ -17,9 +19,7 @@
 #
 # You should have received a copy of the GNU General Public License
 # along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
+# Foundation, Inc.
 
 include $(TOPDIR)/config.mk
 
@@ -42,3 +42,5 @@ $(LIB):	$(obj).depend $(OBJS)
 include $(SRCTREE)/rules.mk
 
 sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/cm_t35/cm_t35.c b/board/compulab/cm_t35/cm_t35.c
index 84c36bafb4..b0b80e5bc9 100644
--- a/board/cm_t35/cm_t35.c
+++ b/board/compulab/cm_t35/cm_t35.c
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2011 CompuLab, Ltd. <www.compulab.co.il>
+ * (C) Copyright 2011 - 2013 CompuLab, Ltd. <www.compulab.co.il>
  *
  * Authors: Mike Rapoport <mike@compulab.co.il>
  *	    Igor Grinberg <grinberg@compulab.co.il>
@@ -448,7 +448,7 @@ int board_mmc_getcd(struct mmc *mmc)
 {
 	u8 val;
 
-	if (twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, &val, TWL4030_BASEADD_GPIO))
+	if (twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO, &val))
 		return -1;
 
 	return !(val & 1);
@@ -493,17 +493,17 @@ static void setup_net_chip_gmpc(void)
 static void reset_net_chip(void)
 {
 	/* Set GPIO1 of TPS65930 as output */
-	twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02,
-				TWL4030_BASEADD_GPIO + 0x03);
+	twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x03,
+			     0x02);
 	/* Send a pulse on the GPIO pin */
-	twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02,
-				TWL4030_BASEADD_GPIO + 0x0C);
+	twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x0C,
+			     0x02);
 	udelay(1);
-	twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02,
-				TWL4030_BASEADD_GPIO + 0x09);
+	twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x09,
+			     0x02);
 	mdelay(40);
-	twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02,
-				TWL4030_BASEADD_GPIO + 0x0C);
+	twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x0C,
+			     0x02);
 	mdelay(1);
 }
 #else
@@ -597,13 +597,13 @@ int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 	udelay(1000);
 
 	offset = TWL4030_BASEADD_GPIO + TWL4030_GPIO_GPIODATADIR1;
-	twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, &val, offset);
+	twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, offset, &val);
 	/* Set GPIO6 and GPIO7 of TPS65930 as output */
 	val |= 0xC0;
-	twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, val, offset);
+	twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, offset, val);
 	offset = TWL4030_BASEADD_GPIO + TWL4030_GPIO_SETGPIODATAOUT1;
 	/* Take both PHYs out of reset */
-	twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0xC0, offset);
+	twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, offset, 0xC0);
 	udelay(1);
 
 	return omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor);
diff --git a/board/cm_t35/display.c b/board/compulab/cm_t35/display.c
index a004ea1d80..adc485365c 100644
--- a/board/cm_t35/display.c
+++ b/board/compulab/cm_t35/display.c
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2012 CompuLab, Ltd. <www.compulab.co.il>
+ * (C) Copyright 2012 - 2013 CompuLab, Ltd. <www.compulab.co.il>
  *
  * Authors: Nikita Kiryanov <nikita@compulab.co.il>
  *
diff --git a/board/cm_t35/eeprom.c b/board/compulab/cm_t35/eeprom.c
index b0af103cdd..b0af103cdd 100644
--- a/board/cm_t35/eeprom.c
+++ b/board/compulab/cm_t35/eeprom.c
diff --git a/board/cm_t35/eeprom.h b/board/compulab/cm_t35/eeprom.h
index 38824d162b..38824d162b 100644
--- a/board/cm_t35/eeprom.h
+++ b/board/compulab/cm_t35/eeprom.h
diff --git a/board/cm_t35/leds.c b/board/compulab/cm_t35/leds.c
index 48ad598d90..dcae135c14 100644
--- a/board/cm_t35/leds.c
+++ b/board/compulab/cm_t35/leds.c
@@ -1,6 +1,5 @@
 /*
- * (C) Copyright 2011
- * CompuLab, Ltd. <www.compulab.co.il>
+ * (C) Copyright 2011 - 2013 CompuLab, Ltd. <www.compulab.co.il>
  *
  * Author: Igor Grinberg <grinberg@compulab.co.il>
  *
diff --git a/board/isee/igep0033/Makefile b/board/isee/igep0033/Makefile
new file mode 100644
index 0000000000..54a4b75252
--- /dev/null
+++ b/board/isee/igep0033/Makefile
@@ -0,0 +1,46 @@
+#
+# Makefile
+#
+# Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed "as is" WITHOUT ANY WARRANTY of any
+# kind, whether express or implied; without even the implied warranty
+# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+ifdef CONFIG_SPL_BUILD
+COBJS	:= mux.o
+endif
+
+COBJS	+= board.o
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/isee/igep0033/board.c b/board/isee/igep0033/board.c
new file mode 100644
index 0000000000..d315516fea
--- /dev/null
+++ b/board/isee/igep0033/board.c
@@ -0,0 +1,232 @@
+/*
+ * Board functions for IGEP COM AQUILA/CYGNUS based boards
+ *
+ * Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <cpsw.h>
+#include "board.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
+#ifdef CONFIG_SPL_BUILD
+static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
+#endif
+
+/* MII mode defines */
+#define RMII_MODE_ENABLE	0x4D
+
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+/* UART Defines */
+#ifdef CONFIG_SPL_BUILD
+#define UART_RESET		(0x1 << 1)
+#define UART_CLK_RUNNING_MASK	0x1
+#define UART_SMART_IDLE_EN	(0x1 << 0x3)
+
+static void rtc32k_enable(void)
+{
+	struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
+
+	/*
+	 * Unlock the RTC's registers.  For more details please see the
+	 * RTC_SS section of the TRM.  In order to unlock we need to
+	 * write these specific values (keys) in this order.
+	 */
+	writel(0x83e70b13, &rtc->kick0r);
+	writel(0x95a4f1e0, &rtc->kick1r);
+
+	/* Enable the RTC 32K OSC by setting bits 3 and 6. */
+	writel((1 << 3) | (1 << 6), &rtc->osc);
+}
+
+static const struct ddr_data ddr3_data = {
+	.datardsratio0 = K4B2G1646EBIH9_RD_DQS,
+	.datawdsratio0 = K4B2G1646EBIH9_WR_DQS,
+	.datafwsratio0 = K4B2G1646EBIH9_PHY_FIFO_WE,
+	.datawrsratio0 = K4B2G1646EBIH9_PHY_WR_DATA,
+	.datadldiff0 = PHY_DLL_LOCK_DIFF,
+};
+
+static const struct cmd_control ddr3_cmd_ctrl_data = {
+	.cmd0csratio = K4B2G1646EBIH9_RATIO,
+	.cmd0dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF,
+	.cmd0iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
+
+	.cmd1csratio = K4B2G1646EBIH9_RATIO,
+	.cmd1dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF,
+	.cmd1iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
+
+	.cmd2csratio = K4B2G1646EBIH9_RATIO,
+	.cmd2dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF,
+	.cmd2iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
+};
+
+static struct emif_regs ddr3_emif_reg_data = {
+	.sdram_config = K4B2G1646EBIH9_EMIF_SDCFG,
+	.ref_ctrl = K4B2G1646EBIH9_EMIF_SDREF,
+	.sdram_tim1 = K4B2G1646EBIH9_EMIF_TIM1,
+	.sdram_tim2 = K4B2G1646EBIH9_EMIF_TIM2,
+	.sdram_tim3 = K4B2G1646EBIH9_EMIF_TIM3,
+	.zq_config = K4B2G1646EBIH9_ZQ_CFG,
+	.emif_ddr_phy_ctlr_1 = K4B2G1646EBIH9_EMIF_READ_LATENCY,
+};
+#endif
+
+/*
+ * Early system init of muxing and clocks.
+ */
+void s_init(void)
+{
+	/* WDT1 is already running when the bootloader gets control
+	 * Disable it to avoid "random" resets
+	 */
+	writel(0xAAAA, &wdtimer->wdtwspr);
+	while (readl(&wdtimer->wdtwwps) != 0x0)
+		;
+	writel(0x5555, &wdtimer->wdtwspr);
+	while (readl(&wdtimer->wdtwwps) != 0x0)
+		;
+
+#ifdef CONFIG_SPL_BUILD
+	/* Setup the PLLs and the clocks for the peripherals */
+	pll_init();
+
+	/* Enable RTC32K clock */
+	rtc32k_enable();
+
+	/* UART softreset */
+	u32 regval;
+
+	enable_uart0_pin_mux();
+
+	regval = readl(&uart_base->uartsyscfg);
+	regval |= UART_RESET;
+	writel(regval, &uart_base->uartsyscfg);
+	while ((readl(&uart_base->uartsyssts) &
+		UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
+		;
+
+	/* Disable smart idle */
+	regval = readl(&uart_base->uartsyscfg);
+	regval |= UART_SMART_IDLE_EN;
+	writel(regval, &uart_base->uartsyscfg);
+
+	gd = &gdata;
+
+	preloader_console_init();
+
+	/* Configure board pin mux */
+	enable_board_pin_mux();
+
+	config_ddr(303, K4B2G1646EBIH9_IOCTRL_VALUE, &ddr3_data,
+		   &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
+#endif
+}
+
+/*
+ * Basic board specific setup.  Pinmux has been handled already.
+ */
+int board_init(void)
+{
+	gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
+
+	gpmc_init();
+
+	return 0;
+}
+
+#if defined(CONFIG_DRIVER_TI_CPSW)
+static void cpsw_control(int enabled)
+{
+	/* VTP can be added here */
+
+	return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+	{
+		.slave_reg_ofs	= 0x208,
+		.sliver_reg_ofs	= 0xd80,
+		.phy_id		= 0,
+		.phy_if		= PHY_INTERFACE_MODE_RMII,
+	},
+};
+
+static struct cpsw_platform_data cpsw_data = {
+	.mdio_base		= CPSW_MDIO_BASE,
+	.cpsw_base		= CPSW_BASE,
+	.mdio_div		= 0xff,
+	.channels		= 8,
+	.cpdma_reg_ofs		= 0x800,
+	.slaves			= 1,
+	.slave_data		= cpsw_slaves,
+	.ale_reg_ofs		= 0xd00,
+	.ale_entries		= 1024,
+	.host_port_reg_ofs	= 0x108,
+	.hw_stats_reg_ofs	= 0x900,
+	.mac_control		= (1 << 5),
+	.control		= cpsw_control,
+	.host_port_num		= 0,
+	.version		= CPSW_CTRL_VERSION_2,
+};
+
+int board_eth_init(bd_t *bis)
+{
+	int rv, ret = 0;
+	uint8_t mac_addr[6];
+	uint32_t mac_hi, mac_lo;
+
+	if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
+		/* try reading mac address from efuse */
+		mac_lo = readl(&cdev->macid0l);
+		mac_hi = readl(&cdev->macid0h);
+		mac_addr[0] = mac_hi & 0xFF;
+		mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+		mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+		mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+		mac_addr[4] = mac_lo & 0xFF;
+		mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+		if (is_valid_ether_addr(mac_addr))
+			eth_setenv_enetaddr("ethaddr", mac_addr);
+	}
+
+	writel(RMII_MODE_ENABLE, &cdev->miisel);
+
+	rv = cpsw_register(&cpsw_data);
+	if (rv < 0)
+		printf("Error %d registering CPSW switch\n", rv);
+	else
+		ret += rv;
+
+	return ret;
+}
+#endif
+
diff --git a/board/isee/igep0033/board.h b/board/isee/igep0033/board.h
new file mode 100644
index 0000000000..37988e0fd3
--- /dev/null
+++ b/board/isee/igep0033/board.h
@@ -0,0 +1,27 @@
+/*
+ * IGEP COM AQUILA/CYGNUS boards information header
+ *
+ * Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * We must be able to enable uart0, for initial output. We then have a
+ * main pinmux function that can be overridden to enable all other pinmux that
+ * is required on the board.
+ */
+void enable_uart0_pin_mux(void);
+void enable_board_pin_mux(void);
+#endif
diff --git a/board/isee/igep0033/mux.c b/board/isee/igep0033/mux.c
new file mode 100644
index 0000000000..16f4addf3d
--- /dev/null
+++ b/board/isee/igep0033/mux.c
@@ -0,0 +1,89 @@
+/*
+ * Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include <i2c.h>
+#include "board.h"
+
+static struct module_pin_mux uart0_pin_mux[] = {
+	{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* UART0_RXD */
+	{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},		/* UART0_TXD */
+	{-1},
+};
+
+static struct module_pin_mux mmc0_pin_mux[] = {
+	{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT3 */
+	{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT2 */
+	{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT1 */
+	{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT0 */
+	{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CLK */
+	{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CMD */
+	{OFFSET(mcasp0_aclkx), (MODE(4) | RXACTIVE)},		/* MMC0_CD */
+	{-1},
+};
+
+static struct module_pin_mux nand_pin_mux[] = {
+	{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD0 */
+	{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD1 */
+	{OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD2 */
+	{OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD3 */
+	{OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD4 */
+	{OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD5 */
+	{OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD6 */
+	{OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD7 */
+	{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
+	{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)},	/* NAND_WPN */
+	{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)},		/* NAND_CS0 */
+	{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)},	/* NAND_ADV_ALE */
+	{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)},	/* NAND_OE */
+	{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)},	/* NAND_WEN */
+	{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)},	/* NAND_BE_CLE */
+	{-1},
+};
+
+static struct module_pin_mux rmii1_pin_mux[] = {
+	{OFFSET(mii1_txen), MODE(1)},			/* RMII1_TXEN */
+	{OFFSET(mii1_rxerr), MODE(1) | RXACTIVE},	/* RMII1_RXERR */
+	{OFFSET(mii1_crs), MODE(1) | RXACTIVE},		/* RMII1_CRS_DV */
+	{OFFSET(mii1_rxd0), MODE(1) | RXACTIVE},	/* RMII1_RXD0 */
+	{OFFSET(mii1_rxd1), MODE(1) | RXACTIVE},	/* RMII1_RXD1 */
+	{OFFSET(mii1_txd0), MODE(1)},			/* RMII1_TXD0 */
+	{OFFSET(mii1_txd1), MODE(1)},			/* RMII1_TXD1 */
+	{OFFSET(rmii1_refclk), MODE(0) | RXACTIVE},	/* RMII1_REF_CLK */
+	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},	/* MDIO_DATA */
+	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},	/* MDIO_CLK */
+	{-1},
+};
+
+void enable_uart0_pin_mux(void)
+{
+	configure_module_pin_mux(uart0_pin_mux);
+}
+
+/*
+ * Do board-specific muxes.
+ */
+void enable_board_pin_mux(void)
+{
+	/* NAND Flash */
+	configure_module_pin_mux(nand_pin_mux);
+	/* SD Card */
+	configure_module_pin_mux(mmc0_pin_mux);
+	/* Ethernet pinmux. */
+	configure_module_pin_mux(rmii1_pin_mux);
+}
+
diff --git a/board/nokia/rx51/rx51.c b/board/nokia/rx51/rx51.c
index 48eb65f896..42bf8b669d 100644
--- a/board/nokia/rx51/rx51.c
+++ b/board/nokia/rx51/rx51.c
@@ -332,10 +332,10 @@ void *video_hw_init(void)
 static void twl4030_regulator_set_mode(u8 id, u8 mode)
 {
 	u16 msg = MSG_SINGULAR(DEV_GRP_P1, id, mode);
-	twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, msg >> 8,
-			TWL4030_PM_MASTER_PB_WORD_MSB);
-	twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, msg & 0xff,
-			TWL4030_PM_MASTER_PB_WORD_LSB);
+	twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER,
+			     TWL4030_PM_MASTER_PB_WORD_MSB, msg >> 8);
+	twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER,
+			     TWL4030_PM_MASTER_PB_WORD_LSB, msg & 0xff);
 }
 
 static void omap3_emu_romcode_call(u32 service_id, u32 *parameters)
@@ -406,12 +406,12 @@ int misc_init_r(void)
 				TWL4030_PM_RECEIVER_DEV_GRP_P1);
 
 	/* store I2C access state */
-	twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER, &state,
-			TWL4030_PM_MASTER_PB_CFG);
+	twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER, TWL4030_PM_MASTER_PB_CFG,
+			    &state);
 
 	/* enable I2C access to powerbus (needed for twl4030 regulator) */
-	twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, 0x02,
-			TWL4030_PM_MASTER_PB_CFG);
+	twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, TWL4030_PM_MASTER_PB_CFG,
+			     0x02);
 
 	/* set VAUX3, VSIM and VMMC1 state to active - enable eMMC memory */
 	twl4030_regulator_set_mode(RES_VAUX3, RES_STATE_ACTIVE);
@@ -419,8 +419,8 @@ int misc_init_r(void)
 	twl4030_regulator_set_mode(RES_VMMC1, RES_STATE_ACTIVE);
 
 	/* restore I2C access state */
-	twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, state,
-			TWL4030_PM_MASTER_PB_CFG);
+	twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, TWL4030_PM_MASTER_PB_CFG,
+			     state);
 
 	/* set env variable attkernaddr for relocated kernel */
 	sprintf(buf, "%#x", KERNEL_ADDRESS);
@@ -475,14 +475,14 @@ void hw_watchdog_reset(void)
 		return;
 
 	/* read actual watchdog timeout */
-	twl4030_i2c_read_u8(TWL4030_CHIP_PM_RECEIVER, &timeout,
-			TWL4030_PM_RECEIVER_WATCHDOG_CFG);
+	twl4030_i2c_read_u8(TWL4030_CHIP_PM_RECEIVER,
+			    TWL4030_PM_RECEIVER_WATCHDOG_CFG, &timeout);
 
 	/* timeout 0 means watchdog is disabled */
 	/* reset watchdog timeout to 31s (maximum) */
 	if (timeout != 0)
-		twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 31,
-				TWL4030_PM_RECEIVER_WATCHDOG_CFG);
+		twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER,
+				     TWL4030_PM_RECEIVER_WATCHDOG_CFG, 31);
 
 	/* store last watchdog reset time */
 	twl_wd_time = get_timer(0);
@@ -531,8 +531,8 @@ int rx51_kp_init(void)
 {
 	int ret = 0;
 	u8 ctrl;
-	ret = twl4030_i2c_read_u8(TWL4030_CHIP_KEYPAD, &ctrl,
-		TWL4030_KEYPAD_KEYP_CTRL_REG);
+	ret = twl4030_i2c_read_u8(TWL4030_CHIP_KEYPAD,
+				  TWL4030_KEYPAD_KEYP_CTRL_REG, &ctrl);
 
 	if (ret)
 		return ret;
@@ -541,18 +541,18 @@ int rx51_kp_init(void)
 	ctrl |= TWL4030_KEYPAD_CTRL_KBD_ON;
 	ctrl |= TWL4030_KEYPAD_CTRL_SOFT_NRST;
 	ctrl |= TWL4030_KEYPAD_CTRL_SOFTMODEN;
-	ret |= twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD, ctrl,
-				TWL4030_KEYPAD_KEYP_CTRL_REG);
+	ret |= twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD,
+				    TWL4030_KEYPAD_KEYP_CTRL_REG, ctrl);
 	/* enable key event status */
-	ret |= twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD, 0xfe,
-				TWL4030_KEYPAD_KEYP_IMR1);
+	ret |= twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD,
+				    TWL4030_KEYPAD_KEYP_IMR1, 0xfe);
 	/* enable interrupt generation on rising and falling */
 	/* this is a workaround for qemu twl4030 emulation */
-	ret |= twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD, 0x57,
-				TWL4030_KEYPAD_KEYP_EDR);
+	ret |= twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD,
+				    TWL4030_KEYPAD_KEYP_EDR, 0x57);
 	/* enable ISR clear on read */
-	ret |= twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD, 0x05,
-				TWL4030_KEYPAD_KEYP_SIH_CTRL);
+	ret |= twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD,
+				    TWL4030_KEYPAD_KEYP_SIH_CTRL, 0x05);
 	return 0;
 }
 
@@ -615,8 +615,8 @@ int rx51_kp_tstc(void)
 	for (i = 0; i < 2; i++) {
 
 		/* check interrupt register for events */
-		twl4030_i2c_read_u8(TWL4030_CHIP_KEYPAD, &intr,
-				TWL4030_KEYPAD_KEYP_ISR1+(2*i));
+		twl4030_i2c_read_u8(TWL4030_CHIP_KEYPAD,
+				    TWL4030_KEYPAD_KEYP_ISR1 + (2 * i), &intr);
 
 		/* no event */
 		if (!(intr&1))
diff --git a/board/pandora/pandora.c b/board/pandora/pandora.c
index 9ff5dd7664..5f0c58d8d2 100644
--- a/board/pandora/pandora.c
+++ b/board/pandora/pandora.c
@@ -114,8 +114,9 @@ int misc_init_r(void)
 
 	/* Enable battery backup capacitor (3.2V, 0.5mA charge current) */
 	twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER,
+		TWL4030_PM_RECEIVER_BB_CFG,
 		TWL4030_BB_CFG_BBCHEN | TWL4030_BB_CFG_BBSEL_3200MV |
-		TWL4030_BB_CFG_BBISEL_500UA, TWL4030_PM_RECEIVER_BB_CFG);
+		TWL4030_BB_CFG_BBISEL_500UA);
 
 	dieid_num_r();
 
diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c
index 3d9b6dd8fd..c686f40a93 100644
--- a/board/ti/beagle/beagle.c
+++ b/board/ti/beagle/beagle.c
@@ -108,13 +108,14 @@ int board_init(void)
 /*
  * Routine: get_board_revision
  * Description: Detect if we are running on a Beagle revision Ax/Bx,
- *		C1/2/3, C4 or xM. This can be done by reading
+ *		C1/2/3, C4, xM Ax/Bx or xM Cx. This can be done by reading
  *		the level of GPIO173, GPIO172 and GPIO171. This should
  *		result in
  *		GPIO173, GPIO172, GPIO171: 1 1 1 => Ax/Bx
  *		GPIO173, GPIO172, GPIO171: 1 1 0 => C1/2/3
  *		GPIO173, GPIO172, GPIO171: 1 0 1 => C4
- *		GPIO173, GPIO172, GPIO171: 0 0 0 => xM
+ *		GPIO173, GPIO172, GPIO171: 0 1 0 => xM Cx
+ *		GPIO173, GPIO172, GPIO171: 0 0 0 => xM Ax/Bx
  */
 static int get_board_revision(void)
 {
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index 7bbb5492fe..bf7e091966 100644
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@@ -27,7 +27,7 @@
  * MA 02111-1307 USA
  */
 #include <common.h>
-#include <twl6035.h>
+#include <palmas.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/mmc_host_def.h>
 
diff --git a/board/ti/omap5_uevm/evm.c b/board/ti/omap5_uevm/evm.c
index 55337c09d5..46db1bfe66 100644
--- a/board/ti/omap5_uevm/evm.c
+++ b/board/ti/omap5_uevm/evm.c
@@ -23,7 +23,7 @@
  * MA 02111-1307 USA
  */
 #include <common.h>
-#include <twl6035.h>
+#include <palmas.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/mmc_host_def.h>
 
@@ -63,8 +63,8 @@ int board_eth_init(bd_t *bis)
  */
 int misc_init_r(void)
 {
-#ifdef CONFIG_TWL6035_POWER
-	twl6035_init_settings();
+#ifdef CONFIG_PALMAS_POWER
+	palmas_init_settings();
 #endif
 	return 0;
 }
diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c
index cab059863d..2bbe392d81 100644
--- a/board/ti/panda/panda.c
+++ b/board/ti/panda/panda.c
@@ -82,6 +82,12 @@ int misc_init_r(void)
 	if (omap_revision() == OMAP4430_ES1_0)
 		return 0;
 
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	if (omap_revision() >= OMAP4460_ES1_0 ||
+		omap_revision() <= OMAP4460_ES1_1)
+		setenv("board_name", strcat(CONFIG_SYS_BOARD, "-es"));
+#endif
+
 	gpio_direction_input(PANDA_ULPI_PHY_TYPE_GPIO);
 	phy_type = gpio_get_value(PANDA_ULPI_PHY_TYPE_GPIO);
 
diff --git a/board/ti/ti814x/evm.c b/board/ti/ti814x/evm.c
index 446e36b844..7adb52405c 100644
--- a/board/ti/ti814x/evm.c
+++ b/board/ti/ti814x/evm.c
@@ -17,6 +17,7 @@
  */
 
 #include <common.h>
+#include <cpsw.h>
 #include <errno.h>
 #include <spl.h>
 #include <asm/arch/cpu.h>
@@ -39,6 +40,8 @@ static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
 static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
 #endif
 
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
 /* UART Defines */
 #ifdef CONFIG_SPL_BUILD
 #define UART_RESET		(0x1 << 1)
@@ -151,6 +154,9 @@ void s_init(void)
 	 */
 	wdt_disable();
 
+	/* Enable timer */
+	timer_init();
+
 	/* Setup the PLLs and the clocks for the peripherals */
 	pll_init();
 
@@ -163,6 +169,9 @@ void s_init(void)
 	/* Set MMC pins */
 	enable_mmc1_pin_mux();
 
+	/* Set Ethernet pins */
+	enable_enet_pin_mux();
+
 	/* Enable UART */
 	uart_enable();
 
@@ -196,3 +205,69 @@ int board_mmc_init(bd_t *bis)
 	return 0;
 }
 #endif
+
+#ifdef CONFIG_DRIVER_TI_CPSW
+static void cpsw_control(int enabled)
+{
+	/* VTP can be added here */
+
+	return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+	{
+		.slave_reg_ofs	= 0x50,
+		.sliver_reg_ofs	= 0x700,
+		.phy_id		= 1,
+	},
+	{
+		.slave_reg_ofs	= 0x90,
+		.sliver_reg_ofs	= 0x740,
+		.phy_id		= 0,
+	},
+};
+
+static struct cpsw_platform_data cpsw_data = {
+	.mdio_base		= CPSW_MDIO_BASE,
+	.cpsw_base		= CPSW_BASE,
+	.mdio_div		= 0xff,
+	.channels		= 8,
+	.cpdma_reg_ofs		= 0x100,
+	.slaves			= 1,
+	.slave_data		= cpsw_slaves,
+	.ale_reg_ofs		= 0x600,
+	.ale_entries		= 1024,
+	.host_port_reg_ofs	= 0x28,
+	.hw_stats_reg_ofs	= 0x400,
+	.mac_control		= (1 << 5),
+	.control		= cpsw_control,
+	.host_port_num		= 0,
+	.version		= CPSW_CTRL_VERSION_1,
+};
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+	uint8_t mac_addr[6];
+	uint32_t mac_hi, mac_lo;
+
+	if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
+		printf("<ethaddr> not set. Reading from E-fuse\n");
+		/* try reading mac address from efuse */
+		mac_lo = readl(&cdev->macid0l);
+		mac_hi = readl(&cdev->macid0h);
+		mac_addr[0] = mac_hi & 0xFF;
+		mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+		mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+		mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+		mac_addr[4] = mac_lo & 0xFF;
+		mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+		if (is_valid_ether_addr(mac_addr))
+			eth_setenv_enetaddr("ethaddr", mac_addr);
+		else
+			printf("Unable to read MAC address. Set <ethaddr>\n");
+	}
+
+	return cpsw_register(&cpsw_data);
+}
diff --git a/board/ti/ti814x/evm.h b/board/ti/ti814x/evm.h
index 40f8710c89..6aebec62d4 100644
--- a/board/ti/ti814x/evm.h
+++ b/board/ti/ti814x/evm.h
@@ -3,5 +3,6 @@
 
 void enable_uart0_pin_mux(void);
 void enable_mmc1_pin_mux(void);
+void enable_enet_pin_mux(void);
 
 #endif /* _EVM_H */
diff --git a/board/ti/ti814x/mux.c b/board/ti/ti814x/mux.c
index 137acb4523..fd9f364511 100644
--- a/board/ti/ti814x/mux.c
+++ b/board/ti/ti814x/mux.c
@@ -40,6 +40,36 @@ static struct module_pin_mux mmc1_pin_mux[] = {
 	{-1},
 };
 
+static struct module_pin_mux enet_pin_mux[] = {
+	{OFFSET(pincntl232), MODE(0x01)},		/* EMAC_RMREFCLK */
+	{OFFSET(pincntl233), PULLUP_EN | MODE(0x01)},	/* MDCLK */
+	{OFFSET(pincntl234), PULLUP_EN | MODE(0x01)},	/* MDIO */
+	{OFFSET(pincntl235), MODE(0x01)},		/* EMAC[0]_MTCLK */
+	{OFFSET(pincntl236), MODE(0x01)},		/* EMAC[0]_MCOL */
+	{OFFSET(pincntl237), MODE(0x01)},		/* EMAC[0]_MCRS */
+	{OFFSET(pincntl238), MODE(0x01)},		/* EMAC[0]_MRXER */
+	{OFFSET(pincntl239), MODE(0x01)},		/* EMAC[0]_MRCLK */
+	{OFFSET(pincntl240), MODE(0x01)},		/* EMAC[0]_MRXD[0] */
+	{OFFSET(pincntl241), MODE(0x01)},		/* EMAC[0]_MRXD[1] */
+	{OFFSET(pincntl242), MODE(0x01)},		/* EMAC[0]_MRXD[2] */
+	{OFFSET(pincntl243), MODE(0x01)},		/* EMAC[0]_MRXD[3] */
+	{OFFSET(pincntl244), MODE(0x01)},		/* EMAC[0]_MRXD[4] */
+	{OFFSET(pincntl245), MODE(0x01)},		/* EMAC[0]_MRXD[5] */
+	{OFFSET(pincntl246), MODE(0x01)},		/* EMAC[0]_MRXD[6] */
+	{OFFSET(pincntl247), MODE(0x01)},		/* EMAC[0]_MRXD[7] */
+	{OFFSET(pincntl248), MODE(0x01)},		/* EMAC[0]_MRXDV */
+	{OFFSET(pincntl249), MODE(0x01)},		/* EMAC[0]_GMTCLK */
+	{OFFSET(pincntl250), MODE(0x01)},		/* EMAC[0]_MTXD[0] */
+	{OFFSET(pincntl251), MODE(0x01)},		/* EMAC[0]_MTXD[1] */
+	{OFFSET(pincntl252), MODE(0x01)},		/* EMAC[0]_MTXD[2] */
+	{OFFSET(pincntl253), MODE(0x01)},		/* EMAC[0]_MTXD[3] */
+	{OFFSET(pincntl254), MODE(0x01)},		/* EMAC[0]_MTXD[4] */
+	{OFFSET(pincntl255), MODE(0x01)},		/* EMAC[0]_MTXD[5] */
+	{OFFSET(pincntl256), MODE(0x01)},		/* EMAC[0]_MTXD[6] */
+	{OFFSET(pincntl257), MODE(0x01)},		/* EMAC[0]_MTXD[7] */
+	{OFFSET(pincntl258), MODE(0x01)},		/* EMAC[0]_MTXEN */
+};
+
 void enable_uart0_pin_mux(void)
 {
 	configure_module_pin_mux(uart0_pin_mux);
@@ -49,3 +79,8 @@ void enable_mmc1_pin_mux(void)
 {
 	configure_module_pin_mux(mmc1_pin_mux);
 }
+
+void enable_enet_pin_mux(void)
+{
+	configure_module_pin_mux(enet_pin_mux);
+}