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authorLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>2020-09-17 15:28:22 +0100
committerMarek Vasut <marek.vasut+renesas@gmail.com>2020-09-26 17:26:01 +0200
commitd03ad060feab99fbcd768b1169129663f8565640 (patch)
tree8d20111e543fe2dbc0603d6e35a969f5245e6896 /board
parent1da91d9bcd6e5ef046c1df0d373d0df87b1e8a72 (diff)
board: renesas: ebisu: Drop CA57 check in reset_cpu()
Renesas Ebisu board is based on R-Car E3 SoC which has dual CA53 and a CR7. This patch drops check for cputype from reset_cpu() and also drops the corresponding CA57 macros. While at it also dropped RST_RSTOUTCR macro which is unused. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Diffstat (limited to 'board')
-rw-r--r--board/renesas/ebisu/ebisu.c15
1 files changed, 1 insertions, 14 deletions
diff --git a/board/renesas/ebisu/ebisu.c b/board/renesas/ebisu/ebisu.c
index d164a36361..b6531f61ed 100644
--- a/board/renesas/ebisu/ebisu.c
+++ b/board/renesas/ebisu/ebisu.c
@@ -47,23 +47,10 @@ int board_init(void)
}
#define RST_BASE 0xE6160000
-#define RST_CA57RESCNT (RST_BASE + 0x40)
#define RST_CA53RESCNT (RST_BASE + 0x44)
-#define RST_RSTOUTCR (RST_BASE + 0x58)
-#define RST_CA57_CODE 0xA5A5000F
#define RST_CA53_CODE 0x5A5A000F
void reset_cpu(ulong addr)
{
- unsigned long midr, cputype;
-
- asm volatile("mrs %0, midr_el1" : "=r" (midr));
- cputype = (midr >> 4) & 0xfff;
-
- if (cputype == 0xd03)
- writel(RST_CA53_CODE, RST_CA53RESCNT);
- else if (cputype == 0xd07)
- writel(RST_CA57_CODE, RST_CA57RESCNT);
- else
- hang();
+ writel(RST_CA53_CODE, RST_CA53RESCNT);
}