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authorMarek Vasut <marex@denx.de>2020-09-13 01:35:08 +0200
committerStefano Babic <sbabic@denx.de>2020-09-17 14:40:55 +0200
commitd1a7205532a34bad2b83451258ca4ccacb9085e4 (patch)
tree932bb5611863a2507f50c0754f2fcdfc11f9b56b /board
parent1189bd513ca376a0f1b357bb0ffec7ae22ace717 (diff)
ARM: mx6: ddr: Add support for iMX6UL/ULL/SL/SDL
This patch adds support for iMX6UL/ULL/SL/SDL MMDC into the DDR calibration code. The difference between MX6DQ and MX6UL/ULL/SL is that the later SoCs have 2 SDQS registers, just like MX6SX, while the MX6DQ/MX6SDL has 8. Fixes: 4f4c128c65 ("ARM: mx6: ddr: Add support for iMX6SX") Signed-off-by: Marek Vasut <marex@denx.de> Cc: Eric Nelson <eric@nelint.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Fabio Estevam <festevam@gmail.com>
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