diff options
| author | Ran Wang <ran.wang_1@nxp.com> | 2020-08-05 15:07:27 +0800 |
|---|---|---|
| committer | Priyanka Jain <priyanka.jain@nxp.com> | 2020-09-24 20:57:32 +0530 |
| commit | 223c19076f8b6808ffcb3772dd91d890d180cd65 (patch) | |
| tree | 54b5dd57c33a1a3322e01af4b0b75ebcb1de9406 /cmd/arm/exception.c | |
| parent | b7585aa9b13b592fbad8b74c4c7c404a7350dd42 (diff) | |
fsl-layerscape: enable dwc3 snooping feature
Configure DWC3’s cache type to ‘cacheable’ for better
performance. Actually related register definition and values are SoC
specific, which means this setting is only applicable to Layerscape SoC,
not generic for all platforms which have integrated DWC3 IP.
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Diffstat (limited to 'cmd/arm/exception.c')
0 files changed, 0 insertions, 0 deletions