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authorParthiban Nallathambi <parthitce@gmail.com>2019-04-18 00:04:09 +0200
committerStefano Babic <sbabic@denx.de>2019-04-25 19:16:24 +0200
commitd8d33b6d4dd2ecd2ea2a3d3ece9e22528d8fd15c (patch)
tree9e5870f0b8e7e6e24d71e15dc8316d35e555d21f /cmd/irq.c
parentb3cf86c86bf00d7d3ee9bc7ecb0819105b641c89 (diff)
imx: Add variscite DART-6UL Evaluation Kit
Port for the DART-6UL Evaluation Kit SBC. Based on the variscite DART-6UL iMX6ULL SoM. CPU: Freescale i.MX6ULL rev1.1 900 MHz (running at 396 MHz) CPU: Commercial temperature grade (0C to 95C) at 43C Reset cause: POR Model: Variscite DART-6UL Evaluation Kit Board: Variscite DART-6UL Evaluation Kit DRAM: 512 MiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 In: serial@02020000 Out: serial@02020000 Err: serial@02020000 Net: FEC0 Working: - Eth0 - i2c - MMC/SD - eMMC - USB host - UART 1 Note: LCDIF porting needs DM_VIDEO https://lists.denx.de/pipermail/u-boot/2019-April/365506.html Signed-off-by: Parthiban Nallathambi <parthitce@gmail.com>
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