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authorYork Sun <yorksun@freescale.com>2011-02-10 10:13:10 -0800
committerKumar Gala <galak@kernel.crashing.org>2011-02-10 23:40:02 -0600
commit856e4b0d7fa366b300bae4f5b9512d7baac6bff1 (patch)
treededbbaa272786a4f7c87971b5f88864452754892 /common/bedbug.c
parentb1d67857af0f66f3def3d0461c141d9b4eccc15e (diff)
powerpc/8xxx: Add additional cycle to write-to-read turnaound for DDR3
When DDR data rate is higher than 1200MT/s or controller interleaving is enabled, additional cycle for write-to-read turnaround is needed to satisfy dynamic ODT timing. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'common/bedbug.c')
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