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| author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2018-07-19 10:13:23 +0900 |
|---|---|---|
| committer | Masahiro Yamada <yamada.masahiro@socionext.com> | 2018-07-25 08:47:52 +0900 |
| commit | 4a610fada193057c97c1b23016ef119f98459b22 (patch) | |
| tree | c4f4944dab0f70d722b0fe73de231ae873ef67ba /common/fdt_support.c | |
| parent | 0dc4addb9111a1587ba9c08594a0f087905a572a (diff) | |
mtd: nand: denali: correct buffer alignment for DMA transfer
The NAND framework makes sure to pass in the buffer with at least
chip->buf_align alignment. Currently, the Denali NAND driver only
requests 16 byte alignment. This causes unaligned cache operations
for the DMA transfer.
[Error Example]
=> nand read 81000010 0 1000
NAND read: device 0 offset 0x0, size 0x1000
CACHE: Misaligned operation at range [81000010, 81001010]
CACHE: Misaligned operation at range [81000010, 81001010]
CACHE: Misaligned operation at range [81000010, 81001010]
CACHE: Misaligned operation at range [81000010, 81001010]
4096 bytes read: OK
Reported-by: Marek Vasut <marex@denx.de>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'common/fdt_support.c')
0 files changed, 0 insertions, 0 deletions