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authorTom Rini <trini@konsulko.com>2019-12-09 21:53:23 -0500
committerTom Rini <trini@konsulko.com>2019-12-09 21:53:23 -0500
commit520f9559020894950d4e962aba52220c8a1d6bfe (patch)
treef39b28ef809b2cd4236803e9e1d7f98c97f0dbd5 /common
parent1045ff4d1af9e3e8a2ad4cf04a7263d49e90cfa7 (diff)
parent0e1233ce9069a87a84a4385de456665d2bc9229d (diff)
Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-riscv
- Increase stack size to avoid a stack overflow during distro boot. - Add hifive-unleashed-a00.dts for SIFIVE FU540. - Add OF_SEPARATE support for SIFIVE FU540. - Add SPL support for Andes AX25 AE350. - Improve U-Boot SPL / OpenSBI smp boot flow for RISC-V.
Diffstat (limited to 'common')
-rw-r--r--common/spl/Kconfig7
-rw-r--r--common/spl/spl_opensbi.c13
2 files changed, 19 insertions, 1 deletions
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index c8cb715c3a..a72412718b 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -439,6 +439,13 @@ config SPL_FIT_IMAGE_TINY
ensure this information is available to the next image
invoked).
+config SPL_CACHE_SUPPORT
+ bool "Support CACHE drivers"
+ help
+ Enable CACHE drivers in SPL. These drivers can keep data so that
+ future requests for that data can be served faster. Enable this option
+ to build the drivers in drivers/cache as part of an SPL build.
+
config SPL_CPU_SUPPORT
bool "Support CPU drivers"
help
diff --git a/common/spl/spl_opensbi.c b/common/spl/spl_opensbi.c
index 2345f949f0..6404373eca 100644
--- a/common/spl/spl_opensbi.c
+++ b/common/spl/spl_opensbi.c
@@ -70,14 +70,25 @@ void spl_invoke_opensbi(struct spl_image_info *spl_image)
opensbi_info.next_addr = uboot_entry;
opensbi_info.next_mode = FW_DYNAMIC_INFO_NEXT_MODE_S;
opensbi_info.options = SBI_SCRATCH_NO_BOOT_PRINTS;
+ opensbi_info.boot_hart = gd->arch.boot_hart;
opensbi_entry = (void (*)(ulong, ulong, ulong))spl_image->entry_point;
invalidate_icache_all();
#ifdef CONFIG_SMP
+ /*
+ * Start OpenSBI on all secondary harts and wait for acknowledgment.
+ *
+ * OpenSBI first relocates itself to its link address. This is done by
+ * the main hart. To make sure no hart is still running U-Boot SPL
+ * during relocation, we wait for all secondary harts to acknowledge
+ * the call-function request before entering OpenSBI on the main hart.
+ * Otherwise, code corruption can occur if the link address ranges of
+ * U-Boot SPL and OpenSBI overlap.
+ */
ret = smp_call_function((ulong)spl_image->entry_point,
(ulong)spl_image->fdt_addr,
- (ulong)&opensbi_info);
+ (ulong)&opensbi_info, 1);
if (ret)
hang();
#endif