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| author | Siarhei Siamashka <siarhei.siamashka@gmail.com> | 2014-08-03 05:32:53 +0300 |
|---|---|---|
| committer | Hans de Goede <hdegoede@redhat.com> | 2014-08-12 08:42:33 +0200 |
| commit | 935758b1d5e58ebd24d8570487455ba286ba4656 (patch) | |
| tree | bad5641247a95850bc592633bd393d1f690b7c98 /configs/BSC9131RDB_SPIFLASH_defconfig | |
| parent | b5c71f5f9c1634d72f40b2c17aeff53ef8fdf8e0 (diff) | |
sunxi: dram: Derive write recovery delay from DRAM clock speed
The write recovery time is 15ns for all JEDEC DDR3 speed bins. And
instead of hardcoding it to 10 cycles, it is possible to set tighter
timings based on accurate calculations. For example, DRAM clock
frequencies up to 533MHz need only 8 cycles for write recovery.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Diffstat (limited to 'configs/BSC9131RDB_SPIFLASH_defconfig')
0 files changed, 0 insertions, 0 deletions