diff options
| author | Icenowy Zheng <icenowy@aosc.io> | 2017-08-14 23:00:11 +0800 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@free-electrons.com> | 2017-10-03 19:12:06 +0200 |
| commit | d4aac530c6ab7d63d362e2836ffa244a91f1765a (patch) | |
| tree | 5f7a7a46f067988f6addbfeead7dd61e97ac9732 /configs/LicheePi_Zero_defconfig | |
| parent | 818b2933055a2d444f43d94e2a7ffce0082fc56b (diff) | |
sunxi: defaultly enable SPL for Lichee Pi Zero
As we have already DRAM initialization code for V3s SoC, we can
defaultly enable SPL now on Lichee Pi Zero.
Add CONFIG_SPL in Lichee Pi Zero defconfig.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Diffstat (limited to 'configs/LicheePi_Zero_defconfig')
| -rw-r--r-- | configs/LicheePi_Zero_defconfig | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/configs/LicheePi_Zero_defconfig b/configs/LicheePi_Zero_defconfig index bd754cb5b3..6cda4ea083 100644 --- a/configs/LicheePi_Zero_defconfig +++ b/configs/LicheePi_Zero_defconfig @@ -4,8 +4,12 @@ CONFIG_MACH_SUN8I_V3S=y CONFIG_DRAM_CLK=360 CONFIG_DRAM_ZQ=14779 CONFIG_DEFAULT_DEVICE_TREE="sun8i-v3s-licheepi-zero" +CONFIG_SPL=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set # CONFIG_NETDEVICES is not set CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_ISO_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set |