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| author | Lokesh Vutla <lokeshvutla@ti.com> | 2019-03-08 11:47:34 +0530 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2019-04-12 08:05:51 -0400 |
| commit | a9a84480f4ccba1eb75c5ca6eb1ff33e8e25fdc4 (patch) | |
| tree | c36dd2fb0dee19399db69d84c1ad79bab13c15c9 /configs/P5020DS_NAND_SECURE_BOOT_defconfig | |
| parent | 6ce424a92022283db31f6ea278eea0d13c67777f (diff) | |
arm: k3: Add support for updating msmc dt node
Certain parts of msmc sram can be used by DMSC or can be
marked as L3 cache. Since the available size can vary, changing
DT every time the size varies might be painful. So, query this
information using TISCI cmd and fixup the DT for kernel.
Fixing up DT does the following:
- Create a sram node if not available
- update the reg property with available size
- update ranges property
- loop through available sub nodes and delete it if:
- mentioned size is out if available range
- subnode represents l3 cache or dmsc usage.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Diffstat (limited to 'configs/P5020DS_NAND_SECURE_BOOT_defconfig')
0 files changed, 0 insertions, 0 deletions