diff options
| author | Suneel Garapati <sgarapati@marvell.com> | 2019-10-19 17:48:25 -0700 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2020-08-25 08:01:16 +0200 |
| commit | 3f6f0cd8fd809287838153d355311f1499040758 (patch) | |
| tree | 4d4dd7e78d49b8bd1d32132f651893fb6e138302 /configs/bcm958622hr_defconfig | |
| parent | 04cd0a0fa03968405918fa6f6b695821767fb068 (diff) | |
ata: ahci: Add BAR index quirk for Cavium PCI SATA device
For SATA controller found on OcteonTX SoC's, use non-standard PCI BAR0
instead of BAR5.
Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'configs/bcm958622hr_defconfig')
0 files changed, 0 insertions, 0 deletions