diff options
| author | Kever Yang <kever.yang@rock-chips.com> | 2019-10-18 15:54:15 +0800 |
|---|---|---|
| committer | Kever Yang <kever.yang@rock-chips.com> | 2019-11-10 20:40:20 +0800 |
| commit | 006ab58d4636124f617174fa2dfe24739874ee91 (patch) | |
| tree | 2ca8b1e300dfa25d610efd644dc863d686b754f8 /configs/chromebook_bob_defconfig | |
| parent | 4b294886d03e9989d6ff163eef04da4927f75952 (diff) | |
rockchip: rk3399: update SPL_STACK_R_ADDR
Use the same SPL_STACK_R_ADDR in Kconfig instead of each board config;
default to 0x4000000(64MB) instead of 0x80000(512KB) for this address
can support all the SoCs including those may have only 64MB memory, and
also reserve enough space for atf, kernel(in falcon mode) loading.
After the ATF entry move to 0x40000, the stack from 0x80000 may be override
when loading ATF bl31.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Diffstat (limited to 'configs/chromebook_bob_defconfig')
| -rw-r--r-- | configs/chromebook_bob_defconfig | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index 8059c633ce..b6e31a4c49 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -8,7 +8,6 @@ CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 # CONFIG_SPL_MMC_SUPPORT is not set CONFIG_TARGET_CHROMEBOOK_BOB=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xff1a0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y |