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authorBrad Griffis <bgriffis@ti.com>2019-04-29 09:59:30 +0530
committerTom Rini <trini@konsulko.com>2019-05-05 08:48:50 -0400
commit6fe3e5ba66ca2a474c46710ebb544a3572b0e64d (patch)
treefc7ad7192bc198dc60adcbf34b424dcafb482bd7 /configs/clearfog_defconfig
parent84cf295f8454156be70958c8dba2c1368942626e (diff)
arm: mach-omap2: am33xx: Enable HW Leveling in the rtc+ddr path
Enable HW leveling in RTC+DDR path. The mandate is to enable HW leveling bit and then wait for 1 ms before accessing any register. Signed-off-by: Brad Griffis <bgriffis@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com>
Diffstat (limited to 'configs/clearfog_defconfig')
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