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authorKever Yang <kever.yang@rock-chips.com>2019-10-18 15:54:14 +0800
committerKever Yang <kever.yang@rock-chips.com>2019-11-10 20:40:20 +0800
commit5ce94c74a6b59922d4280573f2438e4f5f9b29a8 (patch)
treef2d746eafcbf6bfdbbb41c1718b2ef78ad0783e3 /configs/khadas-edge-rk3399_defconfig
parent474197812d1ef924f120ae360d1a7355ebb646ef (diff)
rockchip: rk3399: defconfig: no need to reserve IRAM for SPL
We use to reserve IRAM to avoid the SPL text overlap with ATF M0 code, and when we introduce the TPL, the SPL space is in DRAM, we reserve space to avoid SPL text overlap with ATF bl31. Now we decide to move ATF entry point to 0x40000 instead of 0x1000, so that the SPL can have 0x4000 as code size and no need to reserve space or relocate before loading ATF. The mainline ATF has update since: 0aad563c rockchip: Update BL31_BASE to 0x40000 Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Diffstat (limited to 'configs/khadas-edge-rk3399_defconfig')
-rw-r--r--configs/khadas-edge-rk3399_defconfig1
1 files changed, 0 insertions, 1 deletions
diff --git a/configs/khadas-edge-rk3399_defconfig b/configs/khadas-edge-rk3399_defconfig
index b71fd3a286..c10f710b42 100644
--- a/configs/khadas-edge-rk3399_defconfig
+++ b/configs/khadas-edge-rk3399_defconfig
@@ -2,7 +2,6 @@ CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_ROCKCHIP_RK3399=y
-CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEBUG_UART_BASE=0xFF1A0000