diff options
| author | Patrice Chotard <patrice.chotard@st.com> | 2018-02-08 17:20:47 +0100 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2018-03-13 21:45:37 -0400 |
| commit | 651a70e8d58281fdc034864ad5a8c905e5541c89 (patch) | |
| tree | e232ca28e0a82338535efbce219c0b77b560bd9c /configs/ls1043aqds_defconfig | |
| parent | 526aa92960cfea5d6799b5a6aae89e4e646acc67 (diff) | |
clk: clk_stm32f: No more need of 48Mhz from PLL_SAI
Initially, 48Mhz for SDIO clock was generated from SAI pll for
STM32F469 and STM32F746 SoCs, but this solution was not suitable
for STM32F429 SoCs.
A generic solution is to used the PLL_Q output as 48Mhz clock
for all STM32F SOCs family.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Diffstat (limited to 'configs/ls1043aqds_defconfig')
0 files changed, 0 insertions, 0 deletions