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| author | Lokesh Vutla <lokeshvutla@ti.com> | 2019-09-04 16:01:39 +0530 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2019-10-11 10:07:35 -0400 |
| commit | 293e39780d5f03c3ce8a2b032b607a9cf161d9fc (patch) | |
| tree | a16e5d1d1cd21a05e0e93b059759d4bb7619d0a8 /configs/mx7ulp_evk_defconfig | |
| parent | 55f8eb316979621a229069b60625c5fd580182c4 (diff) | |
arm: dts: k3-j721e-main: Add C66x DSP nodes
The J721E SoCs have two TMS320C66x DSP Core Subsystems (C66x CorePacs)
in the MAIN voltage domain, each with a C66x Fixed/Floating-Point DSP
Core, and 32 KB of L1P & L1D configurable SRAMs/Cache and an additional
288 KB of L2 configurable SRAM/Cache. These subsystems do not have
an MMU but contain a Region Address Translator (RAT) sub-module for
translating 32-bit processor addresses into larger bus addresses.
The inter-processor communication between the main A72 cores and
these processors is achieved through shared memory and Mailboxes.
Add the DT nodes for these DSP processor sub-systems in the common
k3-j721e-main.dtsi file.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Diffstat (limited to 'configs/mx7ulp_evk_defconfig')
0 files changed, 0 insertions, 0 deletions