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| author | Chris Packham <chris.packham@alliedtelesis.co.nz> | 2019-03-01 10:11:13 +1300 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2019-03-19 09:22:05 +0100 |
| commit | 08dcbc98236c4ea9eb4b9d4731a53022204c4809 (patch) | |
| tree | 150b647ed02a9b925602e732fc61fb656c4eb52c /configs/vexpress_ca15_tc2_defconfig | |
| parent | 5860532264326d8eb387ccfd9037792cc6d57fd1 (diff) | |
mv_ddr: ddr3: fix tRAS timimg parameter
Based on the JEDEC standard JESD79-3F. The tRAS timings should include
the highest speed bins at a given frequency. This is similar to commit
683c67b ("mv_ddr: ddr3: fix tfaw timimg parameter") where the wrong
comparison was used in the initial implementation.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
[https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/pull/15]
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'configs/vexpress_ca15_tc2_defconfig')
0 files changed, 0 insertions, 0 deletions