diff options
| author | Tom Rini <trini@konsulko.com> | 2020-06-25 09:33:39 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2020-06-25 09:33:39 -0400 |
| commit | f0e236c8d6646f6ef0ebf8f043962a07dda3b3a3 (patch) | |
| tree | 393f3a5a757c2faf8e1506a6a94e70d253b591dd /configs/xilinx_versal_virt_defconfig | |
| parent | 6ccbd1590fb15b673c90c9ccde5da8dcaaf80a10 (diff) | |
| parent | b8fd54d62f92658cbd20ca051304e13eabf24ddd (diff) | |
Merge tag 'xilinx-for-v2020.10' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next
Xilinx changes for v2020.10
Versal:
- xspi bootmode fix
- Removing one clock from clk driver
- Align u-boot memory setting with OS by default
- Map TCM and OCM by default
ZynqMP:
- Minor DT improvements
- Reduce console buffer for mini configurations
- Add fix for AMS
- Add support for XDP platform
Zynq:
- Support for AES engine
- Enable bigger memory test by default
- Extend documentation for SD preparation
- Use different freq for Topic miami board
mmc:
- minor GD pointer removal
net:
- Support fixed-link cases by zynq gem
- Fix phy looking loop in axi enet driver
spi:
- Cleanup global macros for xilinx spi drivers
firmware:
- Add support for pmufw reloading
fpga:
- Improve error status reporting
common:
- Remove 4kB addition space for FDT allocation
Diffstat (limited to 'configs/xilinx_versal_virt_defconfig')
| -rw-r--r-- | configs/xilinx_versal_virt_defconfig | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index b3e21ea903..3db6c4100c 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -3,11 +3,11 @@ CONFIG_ARCH_VERSAL=y CONFIG_SYS_TEXT_BASE=0x8000000 CONFIG_SYS_MALLOC_F_LEN=0x100000 CONFIG_DM_GPIO=y +CONFIG_DEFINE_TCM_OCM_MMAP=y CONFIG_COUNTER_FREQUENCY=62500000 CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y -# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set CONFIG_BOOTDELAY=5 # CONFIG_DISPLAY_CPUINFO is not set CONFIG_BOARD_EARLY_INIT_R=y |