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authorMichal Simek <michal.simek@xilinx.com>2016-07-14 15:07:54 +0200
committerMichal Simek <michal.simek@xilinx.com>2016-07-22 14:03:54 +0200
commit1f29738ad13ad178185490db0bb17ad71343e251 (patch)
treeedede7e5831e47524f1ebff09dc3bfa7b2d08ae9 /configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
parent1eefe14f66c982bf7145e9d3b57fafd1f17fe12f (diff)
ARM64: zynqmp: Enable CLK and SPL_CLK by default
Serial driver starts to use clk framework that's why enable it by default. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig')
-rw-r--r--configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig2
1 files changed, 0 insertions, 2 deletions
diff --git a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
index 65703481ae..4342e0546b 100644
--- a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
@@ -29,8 +29,6 @@ CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_CLK=y
-CONFIG_SPL_CLK=y
CONFIG_SYS_I2C_CADENCE=y
CONFIG_DM_MMC=y
CONFIG_ZYNQ_SDHCI=y