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authorTom Rini <trini@konsulko.com>2018-09-27 08:29:10 -0400
committerTom Rini <trini@konsulko.com>2018-09-27 08:29:10 -0400
commitbbef20d479441b01d62252cf127498c58078b2c3 (patch)
tree7818d7df29c6147d5270c0ee0a6ff1645917d1b6 /configs/zynq_cse_nand_defconfig
parent0ae8dcfef7c890330c62bb34c724126ffc169bef (diff)
parent3888c8d1979289efe685fe29276aed4d4b685975 (diff)
Merge tag 'xilinx-for-v2018.11' of git://git.denx.de/u-boot-microblaze
Xilinx changes for v2018.11 - Handle BOARD_LATE_INIT via Kconfig SPL: - Enable GZIP for all partitions types(not only for kernel) ZynqMP: - Rearrange pmufw version handling - Support newer PMUFW with improved fpga load sequence Zynq: - Cleanup config file - Simplify zybo config by enabling option via Kconfig net: - Fix gems max-speed property reading - Enable support for fixed-link phys
Diffstat (limited to 'configs/zynq_cse_nand_defconfig')
-rw-r--r--configs/zynq_cse_nand_defconfig1
1 files changed, 1 insertions, 0 deletions
diff --git a/configs/zynq_cse_nand_defconfig b/configs/zynq_cse_nand_defconfig
index ae5a69676d..44ad5bd69c 100644
--- a/configs/zynq_cse_nand_defconfig
+++ b/configs/zynq_cse_nand_defconfig
@@ -6,6 +6,7 @@ CONFIG_ENV_SIZE=0x190
CONFIG_SPL=y
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_SYS_MALLOC_LEN=0x1000
+# CONFIG_BOARD_LATE_INIT is not set
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R=y
CONFIG_SYS_PROMPT="Zynq> "