diff options
| author | Aneesh Bansal <aneesh.bansal@freescale.com> | 2015-06-16 10:36:30 +0530 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2015-07-31 08:50:18 -0700 |
| commit | 73cc2f50eb748475beb004cb37459f1b58e09a09 (patch) | |
| tree | 027d97a08c6dfe33e7dcaceee0dbb5f4b20e0663 /configs | |
| parent | 467a40dfe35f48d830f01a72617207d03ca85b4d (diff) | |
powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P5020 and P5040
Secure Boot Target is added for NAND for P5020 and P5040.
The Secure boot target has already been added for P3041 by
enabling CONFIG_SYS_RAMBOOT and configuring CPC as SRAM.
The targets for P5020 and P5040 are added in the same manner.
Signed-off-by: Saksham Jain <saksham@freescale.com>
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'configs')
| -rw-r--r-- | configs/P5020DS_NAND_SECURE_BOOT_defconfig | 5 | ||||
| -rw-r--r-- | configs/P5040DS_NAND_SECURE_BOOT_defconfig | 5 |
2 files changed, 10 insertions, 0 deletions
diff --git a/configs/P5020DS_NAND_SECURE_BOOT_defconfig b/configs/P5020DS_NAND_SECURE_BOOT_defconfig new file mode 100644 index 0000000000..98cdd35f92 --- /dev/null +++ b/configs/P5020DS_NAND_SECURE_BOOT_defconfig @@ -0,0 +1,5 @@ +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xFFF40000" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P5020DS=y +CONFIG_SPI_FLASH=y diff --git a/configs/P5040DS_NAND_SECURE_BOOT_defconfig b/configs/P5040DS_NAND_SECURE_BOOT_defconfig new file mode 100644 index 0000000000..a6cc7c465e --- /dev/null +++ b/configs/P5040DS_NAND_SECURE_BOOT_defconfig @@ -0,0 +1,5 @@ +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xFFF40000" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P5040DS=y +CONFIG_SPI_FLASH=y |