diff options
| author | Lukas Auer <lukas.auer@aisec.fraunhofer.de> | 2018-11-22 11:26:12 +0100 |
|---|---|---|
| committer | Andes <uboot@andestech.com> | 2018-11-26 13:57:29 +0800 |
| commit | 862e2e75e8f317ff8bd660550d7da3fede2ead09 (patch) | |
| tree | 1c7affaf8b45a246101e92d149e5abc1c85267c1 /configs | |
| parent | 17f2ffea36bf9d2ef7238cfd52b8872cbb50034a (diff) | |
riscv: rename CPU_RISCV_32/64 to match architecture names ARCH_RV32I/64I
RISC-V defines the base integer instruction sets as RV32I and RV64I.
Rename CPU_RISCV_32 and CPU_RISCV_64 to ARCH_RV32I and ARCH_RV64I to
match this convention.
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Diffstat (limited to 'configs')
| -rw-r--r-- | configs/ax25-ae350_defconfig | 2 | ||||
| -rw-r--r-- | configs/qemu-riscv64_defconfig | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/configs/ax25-ae350_defconfig b/configs/ax25-ae350_defconfig index d7c4f40e58..cad82c4213 100644 --- a/configs/ax25-ae350_defconfig +++ b/configs/ax25-ae350_defconfig @@ -1,7 +1,7 @@ CONFIG_RISCV=y CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_TARGET_AX25_AE350=y -CONFIG_CPU_RISCV_64=y +CONFIG_ARCH_RV64I=y CONFIG_DISTRO_DEFAULTS=y CONFIG_NR_DRAM_BANKS=2 CONFIG_FIT=y diff --git a/configs/qemu-riscv64_defconfig b/configs/qemu-riscv64_defconfig index d6c1a5d646..60b647efe8 100644 --- a/configs/qemu-riscv64_defconfig +++ b/configs/qemu-riscv64_defconfig @@ -1,6 +1,6 @@ CONFIG_RISCV=y CONFIG_TARGET_QEMU_VIRT=y -CONFIG_CPU_RISCV_64=y +CONFIG_ARCH_RV64I=y CONFIG_NR_DRAM_BANKS=1 CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y |