diff options
author | wdenk <wdenk> | 2005-04-05 22:30:50 +0000 |
---|---|---|
committer | wdenk <wdenk> | 2005-04-05 22:30:50 +0000 |
commit | b304c96871c92d1ec8fa57dda36cc198660fd10e (patch) | |
tree | b45ea6bbac8eee483d99eccbddda21af57f8e8be /cpu/arm920t | |
parent | 12b43d515c62682fcf7b578f31920a2be49142fe (diff) |
Patches by Steven Scholz, 05 Apr 2005:
- Use i.MX watchdog timer for reset_cpu()
- Move reset_cpu() out of cpu/arm920t/start.S into the SoC specific
subdirectories cpu/arm920t/imx/ and cpu/arm920t/s3c24x0/
(now in interupts.c)
Diffstat (limited to 'cpu/arm920t')
-rw-r--r-- | cpu/arm920t/imx/interrupts.c | 19 | ||||
-rw-r--r-- | cpu/arm920t/s3c24x0/interrupts.c | 27 | ||||
-rw-r--r-- | cpu/arm920t/start.S | 36 |
3 files changed, 46 insertions, 36 deletions
diff --git a/cpu/arm920t/imx/interrupts.c b/cpu/arm920t/imx/interrupts.c index 2f2e754569..03ce06d35a 100644 --- a/cpu/arm920t/imx/interrupts.c +++ b/cpu/arm920t/imx/interrupts.c @@ -117,4 +117,23 @@ ulong get_tbclk (void) return tbclk; } +/* + * Reset the cpu by setting up the watchdog timer and let him time out + */ +void reset_cpu (ulong ignored) +{ + /* Disable watchdog and set Time-Out field to 0 */ + WCR = 0x00000000; + + /* Write Service Sequence */ + WSR = 0x00005555; + WSR = 0x0000AAAA; + + /* Enable watchdog */ + WCR = 0x00000001; + + while (1); + /*NOTREACHED*/ +} + #endif /* defined (CONFIG_IMX) */ diff --git a/cpu/arm920t/s3c24x0/interrupts.c b/cpu/arm920t/s3c24x0/interrupts.c index 868621fa5e..ba835f3caf 100644 --- a/cpu/arm920t/s3c24x0/interrupts.c +++ b/cpu/arm920t/s3c24x0/interrupts.c @@ -185,4 +185,31 @@ ulong get_tbclk (void) return tbclk; } +/* + * reset the cpu by setting up the watchdog timer and let him time out + */ +void reset_cpu (ulong ignored) +{ + S3C24X0_WATCHDOG * const watchdog; + +#ifdef CONFIG_TRAB + disable_vfd(); +#endif + + watchdog = S3C24X0_GetBase_WATCHDOG(); + + /* Disable watchdog */ + watchdog->WTCON = 0x0000; + + /* Initialize watchdog timer count register */ + watchdog->WTCNT = 0x0001; + + /* Enable watchdog timer; assert reset at timer timeout */ + watchdog->WTCON = 0x0021; + + while(1); /* loop forever and wait for reset to happen */ + + /*NOTREACHED*/ +} + #endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */ diff --git a/cpu/arm920t/start.S b/cpu/arm920t/start.S index afe654b8cb..74a97d5290 100644 --- a/cpu/arm920t/start.S +++ b/cpu/arm920t/start.S @@ -433,39 +433,3 @@ fiq: bl do_fiq #endif - - .align 5 -.globl reset_cpu -reset_cpu: -#ifdef CONFIG_S3C2400 - bl disable_interrupts -# ifdef CONFIG_TRAB - bl disable_vfd -# endif - ldr r1, _rWTCON - ldr r2, _rWTCNT - /* Disable watchdog */ - mov r3, #0x0000 - str r3, [r1] - /* Initialize watchdog timer count register */ - mov r3, #0x0001 - str r3, [r2] - /* Enable watchdog timer; assert reset at timer timeout */ - mov r3, #0x0021 - str r3, [r1] -_loop_forever: - b _loop_forever -_rWTCON: - .word 0x15300000 -_rWTCNT: - .word 0x15300008 -#else /* ! CONFIG_S3C2400 */ - mov ip, #0 - mcr p15, 0, ip, c7, c7, 0 @ invalidate cache - mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4) - mrc p15, 0, ip, c1, c0, 0 @ get ctrl register - bic ip, ip, #0x000f @ ............wcam - bic ip, ip, #0x2100 @ ..v....s........ - mcr p15, 0, ip, c1, c0, 0 @ ctrl register - mov pc, r0 -#endif /* CONFIG_S3C2400 */ |