Removes all board specific code from the arch. part for DM644x (DaVinci) boards

Signed-off-by: Pieter Voorthuijsen <pv@prodrive.nl>

2 files changed, 56 insertions, 64 deletions

diff --git a/cpu/arm926ejs/davinci/lowlevel_init.S b/cpu/arm926ejs/davinci/lowlevel_init.S
index a87c112eca..79bc692c14 100644
--- a/cpu/arm926ejs/davinci/lowlevel_init.S
+++ b/cpu/arm926ejs/davinci/lowlevel_init.S
@@ -3,6 +3,11 @@
  *
  * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
  *
+ * Copyright (C) 2008 Prodrive BV <pv@prodrive.nl>
+ * Changed:
+ * Made board specific defines such as DDR timing and PLL
+ * dividers. These should be set in the board config file
+ *
  * Partially based on TI sources, original copyrights follow:
  */
 
@@ -156,17 +161,17 @@ WaitPPL2Loop:
 
 	/* Program the PLL Multiplier */
 	ldr	r6, PLL2_PLLM
-	mov	r2, $0x17	/* 162 MHz */
+	mov	r2, $CFG_DAVINCI_PLL2_PLLM
 	str	r2, [r6]
 
 	/* Program the PLL2 Divisor Value */
 	ldr	r6, PLL2_DIV2
-	mov	r3, $0x01
+	mov	r3, $CFG_DAVINCI_PLL2_DIV2
 	str	r3, [r6]
 
 	/* Program the PLL2 Divisor Value */
 	ldr	r6, PLL2_DIV1
-	mov	r4, $0x0b	/* 54 MHz */
+	mov	r4, $CFG_DAVINCI_PLL2_DIV1
 	str	r4, [r6]
 
 	/* PLL2 DIV2 MMR */
@@ -273,7 +278,7 @@ checkDDRStatClkStop:
 	bne	checkDDRStatClkStop
 
 	/*------------------------------------------------------*
-	 * Program DDR2 MMRs for 162MHz Setting			*
+	 * Program DDR2 MMRs					*
 	 *------------------------------------------------------*/
 
 	/* Program PHY Control Register */
@@ -288,12 +293,12 @@ checkDDRStatClkStop:
 
 	/* Program SDRAM TIM-0 Config Register */
 	ldr	r6, SDTIM0
-	ldr	r7, SDTIM0_VAL_162MHz
+	ldr	r7, SDTIM0_VAL
 	str	r7, [r6]
 
 	/* Program SDRAM TIM-1 Config Register */
 	ldr	r6, SDTIM1
-	ldr	r7, SDTIM1_VAL_162MHz
+	ldr	r7, SDTIM1_VAL
 	str	r7, [r6]
 
 	/* Program the SDRAM Bank Config Control Register */
@@ -435,7 +440,7 @@ WaitLoop:
 
 	/* Program the PLL Multiplier */
 	ldr	r6, PLL1_PLLM
-	mov	r3, $0x15	/* For 594MHz */
+	mov	r3, $CFG_DAVINCI_PLL1_PLLM
 	str	r3, [r6]
 
 	/* Wait for PLL to Reset Properly */
@@ -467,7 +472,7 @@ PLL1Lock:
 	nop
 
 	/*------------------------------------------------------*
-	 * AEMIF configuration for NOR Flash (double check)     *
+	 * AEMIF configuration for NAND/NOR Flash		*
 	 *------------------------------------------------------*/
 	ldr	r0, _PINMUX0
 	ldr	r1, _DEV_SETTING
@@ -479,6 +484,12 @@ PLL1Lock:
 	orr	r2, r2, r1
 	str	r2, [r0]
 
+	ldr	r0, ACFG2
+	ldr	r1, ACFG2_VAL
+	ldr	r2, [r0]
+	and	r1, r2, r1
+	str	r1, [r0]
+
 	ldr	r0, ACFG3
 	ldr	r1, ACFG3_VAL
 	ldr	r2, [r0]
@@ -497,6 +508,12 @@ PLL1Lock:
 	and	r1, r2, r1
 	str	r1, [r0]
 
+	ldr	r0, NANDFCR
+	ldr	r1, NANDFCR_VAL
+	ldr	r2, [r0]
+	and	r1, r2, r1
+	str	r1, [r0]
+
 	/*--------------------------------------*
 	 * VTP manual Calibration               *
 	 *--------------------------------------*/
@@ -560,24 +577,36 @@ _PINMUX1:
 	.word	0x01c40004		/* Device Configuration Registers */
 
 _DEV_SETTING:
-	.word	0x00000c1f
+	.word	CFG_DAVINCI_PINMUX_0
 
 WAITCFG:
 	.word	0x01e00004
 WAITCFG_VAL:
-	.word	0
+	.word	CFG_DAVINCI_WAITCFG
+ACFG2:
+	.word	0x01e00010
+ACFG2_VAL:
+	.word	CFG_DAVINCI_ACFG2
 ACFG3:
 	.word	0x01e00014
 ACFG3_VAL:
-	.word	0x3ffffffd
+	.word	CFG_DAVINCI_ACFG3
 ACFG4:
 	.word	0x01e00018
 ACFG4_VAL:
-	.word	0x3ffffffd
+	.word	CFG_DAVINCI_ACFG4
 ACFG5:
 	.word	0x01e0001c
 ACFG5_VAL:
-	.word	0x3ffffffd
+	.word	CFG_DAVINCI_ACFG5
+NANDFCR:
+	.word	0x01e00060
+NANDFCR_VAL:
+#ifdef CFG_DAVINCI_NANDCE
+	.word	(1 << (CFG_DAVINCI_NANDCE - 2))
+#else
+	.word	0x00000000
+#endif
 
 MDCTL_DDR2:
 	.word	0x01c41a34
@@ -599,33 +628,27 @@ PSC_FLAG_CLEAR:
 PSC_GEM_FLAG_CLEAR:
 	.word	0xfffffeff
 
-/* DDR2 MMR & CONFIGURATION VALUES, 162 MHZ clock */
+/* DDR2 MMR & CONFIGURATION VALUES */
 DDRCTL:
 	.word	0x200000e4
 DDRCTL_VAL:
-	.word	0x50006405
+	.word	CFG_DAVINCI_DDRCTL
 SDREF:
 	.word	0x2000000c
 SDREF_VAL:
-	.word	0x000005c3
+	.word	CFG_DAVINCI_SDREF
 SDCFG:
 	.word	0x20000008
 SDCFG_VAL:
-#ifdef	DDR_4BANKS
-	.word	0x00178622
-#elif defined DDR_8BANKS
-	.word	0x00178632
-#else
-#error "Unknown DDR configuration!!!"
-#endif
+	.word	CFG_DAVINCI_SDCFG
 SDTIM0:
 	.word	0x20000010
-SDTIM0_VAL_162MHz:
-	.word	0x28923211
+SDTIM0_VAL:
+	.word	CFG_DAVINCI_SDTIM0
 SDTIM1:
 	.word	0x20000014
-SDTIM1_VAL_162MHz:
-	.word	0x0016c722
+SDTIM1_VAL:
+	.word	CFG_DAVINCI_SDTIM1
 VTPIOCR:
 	.word	0x200000f0	/* VTP IO Control register */
 DDRVTPR:
@@ -699,7 +722,7 @@ PLL2_DIV_MASK:
 MMARG_BRF0:
 	.word	0x01c42010	/* BRF margin mode 0 (R/W)*/
 MMARG_BRF0_VAL:
-	.word	0x00444400
+	.word	CFG_DAVINCI_MMARG_BRF0
 
 DDR2_START_ADDR:
 	.word	0x80000000
diff --git a/cpu/arm926ejs/davinci/nand.c b/cpu/arm926ejs/davinci/nand.c
index 127be9fcd4..3257f83a2f 100644
--- a/cpu/arm926ejs/davinci/nand.c
+++ b/cpu/arm926ejs/davinci/nand.c
@@ -117,7 +117,7 @@ static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
 	dummy = emif_addr->NANDF3ECC;
 	dummy = emif_addr->NANDF4ECC;
 
-	emif_addr->NANDFCR |= (1 << 8);
+	emif_addr->NANDFCR |= (1 << (CFG_DAVINCI_NANDCE + 6));
 }
 
 static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region)
@@ -147,7 +147,7 @@ static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u
 
 	n = (this->eccmode == NAND_ECC_HW12_2048) ? 4 : 1;
 
-	region = 1;
+	region = (CFG_DAVINCI_NANDCE - 1);
 	while (n--) {
 		tmp = nand_davinci_readecc(mtd, region);
 		*ecc_code++ = tmp;
@@ -311,40 +311,9 @@ static int nand_davinci_waitfunc(struct mtd_info *mtd, struct nand_chip *this, i
 
 static void nand_flash_init(void)
 {
-	u_int32_t	acfg1 = 0x3ffffffc;
-	u_int32_t	acfg2 = 0x3ffffffc;
-	u_int32_t	acfg3 = 0x3ffffffc;
-	u_int32_t	acfg4 = 0x3ffffffc;
-	emifregs	emif_regs;
-
-	/*------------------------------------------------------------------*
-	 *  NAND FLASH CHIP TIMEOUT @ 459 MHz                               *
-	 *                                                                  *
-	 *  AEMIF.CLK freq   = PLL1/6 = 459/6 = 76.5 MHz                    *
-	 *  AEMIF.CLK period = 1/76.5 MHz = 13.1 ns                         *
-	 *                                                                  *
-	 *------------------------------------------------------------------*/
-	 acfg1 = 0
-	 	| (0 << 31 )	/* selectStrobe */
-	 	| (0 << 30 )	/* extWait */
-	 	| (1 << 26 )	/* writeSetup	10 ns */
-	 	| (3 << 20 )	/* writeStrobe	40 ns */
-	 	| (1 << 17 )	/* writeHold	10 ns */
-	 	| (1 << 13 )	/* readSetup	10 ns */
-	 	| (5 << 7 )	/* readStrobe	60 ns */
-	 	| (1 << 4 )	/* readHold	10 ns */
-	 	| (3 << 2 )	/* turnAround	?? ns */
-	 	| (0 << 0 )	/* asyncSize	8-bit bus */
-	 	;
-
-	emif_regs = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE;
-
-	emif_regs->AWCCR |= 0x10000000;
-	emif_regs->AB1CR = acfg1;	/* 0x08244128 */;
-	emif_regs->AB2CR = acfg2;
-	emif_regs->AB3CR = acfg3;
-	emif_regs->AB4CR = acfg4;
-	emif_regs->NANDFCR = 0x00000101;
+	/* All EMIF initialization is done in lowlevel_init.S
+	 * and config values are in the board config files
+	 */
 }
 
 int board_nand_init(struct nand_chip *nand)