arm: Move cpu/$CPU to arch/arm/cpu/$CPU

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>

59 files changed, 0 insertions, 7714 deletions

diff --git a/cpu/arm926ejs/Makefile b/cpu/arm926ejs/Makefile
deleted file mode 100644
index 7701b03bbe..0000000000
--- a/cpu/arm926ejs/Makefile
+++ /dev/null
@@ -1,47 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(CPU).a
-
-START	= start.o
-COBJS	= cpu.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS)
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/cpu/arm926ejs/at91/Makefile b/cpu/arm926ejs/at91/Makefile
deleted file mode 100644
index 4f467be91c..0000000000
--- a/cpu/arm926ejs/at91/Makefile
+++ /dev/null
@@ -1,62 +0,0 @@
-#
-# (C) Copyright 2000-2008
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).a
-
-COBJS-$(CONFIG_AT91CAP9)	+= at91cap9_devices.o
-COBJS-$(CONFIG_AT91SAM9260)	+= at91sam9260_devices.o
-COBJS-$(CONFIG_AT91SAM9G20)	+= at91sam9260_devices.o
-COBJS-$(CONFIG_AT91SAM9261)	+= at91sam9261_devices.o
-COBJS-$(CONFIG_AT91SAM9G10)	+= at91sam9261_devices.o
-COBJS-$(CONFIG_AT91SAM9263)	+= at91sam9263_devices.o
-COBJS-$(CONFIG_AT91SAM9RL)	+= at91sam9rl_devices.o
-COBJS-$(CONFIG_AT91SAM9M10G45)	+= at91sam9m10g45_devices.o
-COBJS-$(CONFIG_AT91SAM9G45)	+= at91sam9m10g45_devices.o
-COBJS-$(CONFIG_AT91_LED)	+= led.o
-COBJS-y += clock.o
-COBJS-y += cpu.o
-COBJS-y	+= reset.o
-COBJS-y	+= timer.o
-
-ifndef CONFIG_SKIP_LOWLEVEL_INIT
-SOBJS-y	:= lowlevel_init.o
-endif
-
-SRCS    := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS    := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS)
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/cpu/arm926ejs/at91/at91cap9_devices.c b/cpu/arm926ejs/at91/at91cap9_devices.c
deleted file mode 100644
index 2d878fdde6..0000000000
--- a/cpu/arm926ejs/at91/at91cap9_devices.c
+++ /dev/null
@@ -1,205 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian.pop@leadtechdesign.com>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * (C) Copyright 2009
- * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
- * esd electronic system design gmbh <www.esd.eu>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/io.h>
-
-void at91_serial0_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTA, 22, 1);		/* TXD0 */
-	at91_set_a_periph(AT91_PIO_PORTA, 23, 0);		/* RXD0 */
-	writel(1 << AT91CAP9_ID_US0, &pmc->pcer);
-}
-
-void at91_serial1_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTD, 0, 1);		/* TXD1 */
-	at91_set_a_periph(AT91_PIO_PORTD, 1, 0);		/* RXD1 */
-	writel(1 << AT91CAP9_ID_US1, &pmc->pcer);
-}
-
-void at91_serial2_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTD, 2, 1);		/* TXD2 */
-	at91_set_a_periph(AT91_PIO_PORTD, 3, 0);		/* RXD2 */
-	writel(1 << AT91CAP9_ID_US2, &pmc->pcer);
-}
-
-void at91_serial3_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTC, 30, 0);		/* DRXD */
-	at91_set_a_periph(AT91_PIO_PORTC, 31, 1);		/* DTXD */
-	writel(1 << AT91_ID_SYS, &pmc->pcer);
-}
-
-void at91_serial_hw_init(void)
-{
-#ifdef CONFIG_USART0
-	at91_serial0_hw_init();
-#endif
-
-#ifdef CONFIG_USART1
-	at91_serial1_hw_init();
-#endif
-
-#ifdef CONFIG_USART2
-	at91_serial2_hw_init();
-#endif
-
-#ifdef CONFIG_USART3	/* DBGU */
-	at91_serial3_hw_init();
-#endif
-}
-
-#ifdef CONFIG_HAS_DATAFLASH
-void at91_spi0_hw_init(unsigned long cs_mask)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_b_periph(AT91_PIO_PORTA, 0, 0);	/* SPI0_MISO */
-	at91_set_b_periph(AT91_PIO_PORTA, 1, 0);	/* SPI0_MOSI */
-	at91_set_b_periph(AT91_PIO_PORTA, 2, 0);	/* SPI0_SPCK */
-
-	/* Enable clock */
-	writel(1 << AT91CAP9_ID_SPI0, &pmc->pcer);
-
-	if (cs_mask & (1 << 0)) {
-		at91_set_b_periph(AT91_PIO_PORTA, 5, 1);
-	}
-	if (cs_mask & (1 << 1)) {
-		at91_set_b_periph(AT91_PIO_PORTA, 3, 1);
-	}
-	if (cs_mask & (1 << 2)) {
-		at91_set_b_periph(AT91_PIO_PORTD, 0, 1);
-	}
-	if (cs_mask & (1 << 3)) {
-		at91_set_b_periph(AT91_PIO_PORTD, 1, 1);
-	}
-	if (cs_mask & (1 << 4)) {
-		at91_set_pio_output(AT91_PIO_PORTA, 5, 1);
-	}
-	if (cs_mask & (1 << 5)) {
-		at91_set_pio_output(AT91_PIO_PORTA, 3, 1);
-	}
-	if (cs_mask & (1 << 6)) {
-		at91_set_pio_output(AT91_PIO_PORTD, 0, 1);
-	}
-	if (cs_mask & (1 << 7)) {
-		at91_set_pio_output(AT91_PIO_PORTD, 1, 1);
-	}
-}
-
-void at91_spi1_hw_init(unsigned long cs_mask)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTB, 12, 0);	/* SPI1_MISO */
-	at91_set_a_periph(AT91_PIO_PORTB, 13, 0);	/* SPI1_MOSI */
-	at91_set_a_periph(AT91_PIO_PORTB, 14, 0);	/* SPI1_SPCK */
-
-	/* Enable clock */
-	writel(1 << AT91CAP9_ID_SPI1, &pmc->pcer);
-
-	if (cs_mask & (1 << 0)) {
-		at91_set_a_periph(AT91_PIO_PORTB, 15, 1);
-	}
-	if (cs_mask & (1 << 1)) {
-		at91_set_a_periph(AT91_PIO_PORTB, 16, 1);
-	}
-	if (cs_mask & (1 << 2)) {
-		at91_set_a_periph(AT91_PIO_PORTB, 17, 1);
-	}
-	if (cs_mask & (1 << 3)) {
-		at91_set_a_periph(AT91_PIO_PORTB, 18, 1);
-	}
-	if (cs_mask & (1 << 4)) {
-		at91_set_pio_output(AT91_PIO_PORTB, 15, 1);
-	}
-	if (cs_mask & (1 << 5)) {
-		at91_set_pio_output(AT91_PIO_PORTB, 16, 1);
-	}
-	if (cs_mask & (1 << 6)) {
-		at91_set_pio_output(AT91_PIO_PORTB, 17, 1);
-	}
-	if (cs_mask & (1 << 7)) {
-		at91_set_pio_output(AT91_PIO_PORTB, 18, 1);
-	}
-
-}
-#endif
-
-#ifdef CONFIG_MACB
-void at91_macb_hw_init(void)
-{
-	at91_set_a_periph(AT91_PIO_PORTB, 21, 0);	/* ETXCK_EREFCK */
-	at91_set_a_periph(AT91_PIO_PORTB, 22, 0);	/* ERXDV */
-	at91_set_a_periph(AT91_PIO_PORTB, 25, 0);	/* ERX0 */
-	at91_set_a_periph(AT91_PIO_PORTB, 26, 0);	/* ERX1 */
-	at91_set_a_periph(AT91_PIO_PORTB, 27, 0);	/* ERXER */
-	at91_set_a_periph(AT91_PIO_PORTB, 28, 0);	/* ETXEN */
-	at91_set_a_periph(AT91_PIO_PORTB, 23, 0);	/* ETX0 */
-	at91_set_a_periph(AT91_PIO_PORTB, 24, 0);	/* ETX1 */
-	at91_set_a_periph(AT91_PIO_PORTB, 30, 0);	/* EMDIO */
-	at91_set_a_periph(AT91_PIO_PORTB, 29, 0);	/* EMDC */
-
-#ifndef CONFIG_RMII
-	at91_set_b_periph(AT91_PIO_PORTC, 25, 0);	/* ECRS */
-	at91_set_b_periph(AT91_PIO_PORTC, 26, 0);	/* ECOL */
-	at91_set_b_periph(AT91_PIO_PORTC, 22, 0);	/* ERX2 */
-	at91_set_b_periph(AT91_PIO_PORTC, 23, 0);	/* ERX3 */
-	at91_set_b_periph(AT91_PIO_PORTC, 27, 0);	/* ERXCK */
-	at91_set_b_periph(AT91_PIO_PORTC, 20, 0);	/* ETX2 */
-	at91_set_b_periph(AT91_PIO_PORTC, 21, 0);	/* ETX3 */
-	at91_set_b_periph(AT91_PIO_PORTC, 24, 0);	/* ETXER */
-#endif
-}
-#endif
-
-#ifdef CONFIG_AT91_CAN
-void at91_can_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTA, 12, 0);	/* CAN_TX */
-	at91_set_a_periph(AT91_PIO_PORTA, 13, 1);	/* CAN_RX */
-
-	/* Enable clock */
-	writel(1 << AT91CAP9_ID_CAN, &pmc->pcer);
-}
-#endif
diff --git a/cpu/arm926ejs/at91/at91sam9260_devices.c b/cpu/arm926ejs/at91/at91sam9260_devices.c
deleted file mode 100644
index 77d49ab1c7..0000000000
--- a/cpu/arm926ejs/at91/at91sam9260_devices.c
+++ /dev/null
@@ -1,196 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian.pop@leadtechdesign.com>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/io.h>
-
-void at91_serial0_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTB, 4, 1);		/* TXD0 */
-	at91_set_a_periph(AT91_PIO_PORTB, 5, 0);		/* RXD0 */
-	writel(1 << AT91SAM9260_ID_US0, &pmc->pcer);
-}
-
-void at91_serial1_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTB, 6, 1);		/* TXD1 */
-	at91_set_a_periph(AT91_PIO_PORTB, 7, 0);		/* RXD1 */
-	writel(1 << AT91SAM9260_ID_US1, &pmc->pcer);
-}
-
-void at91_serial2_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTB, 8, 1);		/* TXD2 */
-	at91_set_a_periph(AT91_PIO_PORTB, 9, 0);		/* RXD2 */
-	writel(1 << AT91SAM9260_ID_US2, &pmc->pcer);
-}
-
-void at91_serial3_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTB, 14, 0);		/* DRXD */
-	at91_set_a_periph(AT91_PIO_PORTB, 15, 1);		/* DTXD */
-	writel(1 << AT91_ID_SYS, &pmc->pcer);
-}
-
-void at91_serial_hw_init(void)
-{
-#ifdef CONFIG_USART0
-	at91_serial0_hw_init();
-#endif
-
-#ifdef CONFIG_USART1
-	at91_serial1_hw_init();
-#endif
-
-#ifdef CONFIG_USART2
-	at91_serial2_hw_init();
-#endif
-
-#ifdef CONFIG_USART3	/* DBGU */
-	at91_serial3_hw_init();
-#endif
-}
-
-#if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI)
-void at91_spi0_hw_init(unsigned long cs_mask)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTA, 0, 0);	/* SPI0_MISO */
-	at91_set_a_periph(AT91_PIO_PORTA, 1, 0);	/* SPI0_MOSI */
-	at91_set_a_periph(AT91_PIO_PORTA, 2, 0);	/* SPI0_SPCK */
-
-	/* Enable clock */
-	writel(1 << AT91SAM9260_ID_SPI0, &pmc->pcer);
-
-	if (cs_mask & (1 << 0)) {
-		at91_set_a_periph(AT91_PIO_PORTA, 3, 1);
-	}
-	if (cs_mask & (1 << 1)) {
-		at91_set_b_periph(AT91_PIO_PORTC, 11, 1);
-	}
-	if (cs_mask & (1 << 2)) {
-		at91_set_b_periph(AT91_PIO_PORTC, 16, 1);
-	}
-	if (cs_mask & (1 << 3)) {
-		at91_set_b_periph(AT91_PIO_PORTC, 17, 1);
-	}
-	if (cs_mask & (1 << 4)) {
-		at91_set_pio_output(AT91_PIO_PORTA, 3, 1);
-	}
-	if (cs_mask & (1 << 5)) {
-		at91_set_pio_output(AT91_PIO_PORTC, 11, 1);
-	}
-	if (cs_mask & (1 << 6)) {
-		at91_set_pio_output(AT91_PIO_PORTC, 16, 1);
-	}
-	if (cs_mask & (1 << 7)) {
-		at91_set_pio_output(AT91_PIO_PORTC, 17, 1);
-	}
-}
-
-void at91_spi1_hw_init(unsigned long cs_mask)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTB, 0, 0);	/* SPI1_MISO */
-	at91_set_a_periph(AT91_PIO_PORTB, 1, 0);	/* SPI1_MOSI */
-	at91_set_a_periph(AT91_PIO_PORTB, 2, 0);	/* SPI1_SPCK */
-
-	/* Enable clock */
-	writel(1 << AT91SAM9260_ID_SPI1, &pmc->pcer);
-
-	if (cs_mask & (1 << 0)) {
-		at91_set_a_periph(AT91_PIO_PORTB, 3, 1);
-	}
-	if (cs_mask & (1 << 1)) {
-		at91_set_b_periph(AT91_PIO_PORTC, 5, 1);
-	}
-	if (cs_mask & (1 << 2)) {
-		at91_set_b_periph(AT91_PIO_PORTC, 4, 1);
-	}
-	if (cs_mask & (1 << 3)) {
-		at91_set_pio_output(AT91_PIO_PORTC, 3, 1);
-	}
-	if (cs_mask & (1 << 4)) {
-		at91_set_pio_output(AT91_PIO_PORTB, 3, 1);
-	}
-	if (cs_mask & (1 << 5)) {
-		at91_set_pio_output(AT91_PIO_PORTC, 5, 1);
-	}
-	if (cs_mask & (1 << 6)) {
-		at91_set_pio_output(AT91_PIO_PORTC, 4, 1);
-	}
-	if (cs_mask & (1 << 7)) {
-		at91_set_pio_output(AT91_PIO_PORTC, 3, 1);
-	}
-}
-#endif
-
-#ifdef CONFIG_MACB
-void at91_macb_hw_init(void)
-{
-	at91_set_a_periph(AT91_PIO_PORTA, 19, 0);	/* ETXCK_EREFCK */
-	at91_set_a_periph(AT91_PIO_PORTA, 17, 0);	/* ERXDV */
-	at91_set_a_periph(AT91_PIO_PORTA, 14, 0);	/* ERX0 */
-	at91_set_a_periph(AT91_PIO_PORTA, 15, 0);	/* ERX1 */
-	at91_set_a_periph(AT91_PIO_PORTA, 18, 0);	/* ERXER */
-	at91_set_a_periph(AT91_PIO_PORTA, 16, 0);	/* ETXEN */
-	at91_set_a_periph(AT91_PIO_PORTA, 12, 0);	/* ETX0 */
-	at91_set_a_periph(AT91_PIO_PORTA, 13, 0);	/* ETX1 */
-	at91_set_a_periph(AT91_PIO_PORTA, 21, 0);	/* EMDIO */
-	at91_set_a_periph(AT91_PIO_PORTA, 20, 0);	/* EMDC */
-
-#ifndef CONFIG_RMII
-	at91_set_b_periph(AT91_PIO_PORTA, 28, 0);	/* ECRS */
-	at91_set_b_periph(AT91_PIO_PORTA, 29, 0);	/* ECOL */
-	at91_set_b_periph(AT91_PIO_PORTA, 25, 0);	/* ERX2 */
-	at91_set_b_periph(AT91_PIO_PORTA, 26, 0);	/* ERX3 */
-	at91_set_b_periph(AT91_PIO_PORTA, 27, 0);	/* ERXCK */
-#if defined(CONFIG_AT91SAM9260EK) || defined(CONFIG_AFEB9260)
-	/*
-	 * use PA10, PA11 for ETX2, ETX3.
-	 * PA23 and PA24 are for TWI EEPROM
-	 */
-	at91_set_b_periph(AT91_PIO_PORTA, 10, 0);	/* ETX2 */
-	at91_set_b_periph(AT91_PIO_PORTA, 11, 0);	/* ETX3 */
-#else
-	at91_set_b_periph(AT91_PIO_PORTA, 23, 0);	/* ETX2 */
-	at91_set_b_periph(AT91_PIO_PORTA, 24, 0);	/* ETX3 */
-#endif
-	at91_set_b_periph(AT91_PIO_PORTA, 22, 0);	/* ETXER */
-#endif
-}
-#endif
diff --git a/cpu/arm926ejs/at91/at91sam9261_devices.c b/cpu/arm926ejs/at91/at91sam9261_devices.c
deleted file mode 100644
index b4353ef5cb..0000000000
--- a/cpu/arm926ejs/at91/at91sam9261_devices.c
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian.pop@leadtechdesign.com>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/io.h>
-
-void at91_serial0_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTC, 8, 1);		/* TXD0 */
-	at91_set_a_periph(AT91_PIO_PORTC, 9, 0);		/* RXD0 */
-	writel(1 << AT91SAM9261_ID_US0, &pmc->pcer);
-}
-
-void at91_serial1_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTC, 12, 1);		/* TXD1 */
-	at91_set_a_periph(AT91_PIO_PORTC, 13, 0);		/* RXD1 */
-	writel(1 << AT91SAM9261_ID_US1, &pmc->pcer);
-}
-
-void at91_serial2_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTC, 14, 1);		/* TXD2 */
-	at91_set_a_periph(AT91_PIO_PORTC, 15, 0);		/* RXD2 */
-	writel(1 << AT91SAM9261_ID_US2, &pmc->pcer);
-}
-
-void at91_serial3_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTA, 9, 0);		/* DRXD */
-	at91_set_a_periph(AT91_PIO_PORTA, 10, 1);		/* DTXD */
-	writel(1 << AT91_ID_SYS, &pmc->pcer);
-}
-
-void at91_serial_hw_init(void)
-{
-#ifdef CONFIG_USART0
-	at91_serial0_hw_init();
-#endif
-
-#ifdef CONFIG_USART1
-	at91_serial1_hw_init();
-#endif
-
-#ifdef CONFIG_USART2
-	at91_serial2_hw_init();
-#endif
-
-#ifdef CONFIG_USART3	/* DBGU */
-	at91_serial3_hw_init();
-#endif
-}
-
-#ifdef CONFIG_HAS_DATAFLASH
-void at91_spi0_hw_init(unsigned long cs_mask)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTA, 0, 0);	/* SPI0_MISO */
-	at91_set_a_periph(AT91_PIO_PORTA, 1, 0);	/* SPI0_MOSI */
-	at91_set_a_periph(AT91_PIO_PORTA, 2, 0);	/* SPI0_SPCK */
-
-	/* Enable clock */
-	writel(1 << AT91SAM9261_ID_SPI0, &pmc->pcer);
-
-	if (cs_mask & (1 << 0)) {
-		at91_set_a_periph(AT91_PIO_PORTA, 3, 1);
-	}
-	if (cs_mask & (1 << 1)) {
-		at91_set_a_periph(AT91_PIO_PORTA, 4, 1);
-	}
-	if (cs_mask & (1 << 2)) {
-		at91_set_a_periph(AT91_PIO_PORTA, 5, 1);
-	}
-	if (cs_mask & (1 << 3)) {
-		at91_set_a_periph(AT91_PIO_PORTA, 6, 1);
-	}
-	if (cs_mask & (1 << 4)) {
-		at91_set_pio_output(AT91_PIO_PORTA, 3, 1);
-	}
-	if (cs_mask & (1 << 5)) {
-		at91_set_pio_output(AT91_PIO_PORTA, 4, 1);
-	}
-	if (cs_mask & (1 << 6)) {
-		at91_set_pio_output(AT91_PIO_PORTA, 5, 1);
-	}
-	if (cs_mask & (1 << 7)) {
-		at91_set_pio_output(AT91_PIO_PORTA, 6, 1);
-	}
-}
-
-void at91_spi1_hw_init(unsigned long cs_mask)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTB, 30, 0);	/* SPI1_MISO */
-	at91_set_a_periph(AT91_PIO_PORTB, 31, 0);	/* SPI1_MOSI */
-	at91_set_a_periph(AT91_PIO_PORTB, 29, 0);	/* SPI1_SPCK */
-
-	/* Enable clock */
-	writel(1 << AT91SAM9261_ID_SPI1, &pmc->pcer);
-
-	if (cs_mask & (1 << 0)) {
-		at91_set_a_periph(AT91_PIO_PORTB, 28, 1);
-	}
-	if (cs_mask & (1 << 1)) {
-		at91_set_b_periph(AT91_PIO_PORTA, 24, 1);
-	}
-	if (cs_mask & (1 << 2)) {
-		at91_set_b_periph(AT91_PIO_PORTA, 25, 1);
-	}
-	if (cs_mask & (1 << 3)) {
-		at91_set_a_periph(AT91_PIO_PORTA, 26, 1);
-	}
-	if (cs_mask & (1 << 4)) {
-		at91_set_pio_output(AT91_PIO_PORTB, 28, 1);
-	}
-	if (cs_mask & (1 << 5)) {
-		at91_set_pio_output(AT91_PIO_PORTA, 24, 1);
-	}
-	if (cs_mask & (1 << 6)) {
-		at91_set_pio_output(AT91_PIO_PORTA, 25, 1);
-	}
-	if (cs_mask & (1 << 7)) {
-		at91_set_pio_output(AT91_PIO_PORTA, 26, 1);
-	}
-}
-#endif
diff --git a/cpu/arm926ejs/at91/at91sam9263_devices.c b/cpu/arm926ejs/at91/at91sam9263_devices.c
deleted file mode 100644
index deda3e54d9..0000000000
--- a/cpu/arm926ejs/at91/at91sam9263_devices.c
+++ /dev/null
@@ -1,214 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian.pop@leadtechdesign.com>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * (C) Copyright 2009
- * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
- * esd electronic system design gmbh <www.esd.eu>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/io.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_pio.h>
-
-void at91_serial0_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTA, 26, 1);		/* TXD0 */
-	at91_set_a_periph(AT91_PIO_PORTA, 27, 0);		/* RXD0 */
-	writel(1 << AT91SAM9263_ID_US0, &pmc->pcer);
-}
-
-void at91_serial1_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTD, 0, 1);		/* TXD1 */
-	at91_set_a_periph(AT91_PIO_PORTD, 1, 0);		/* RXD1 */
-	writel(1 << AT91SAM9263_ID_US1, &pmc->pcer);
-}
-
-void at91_serial2_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTD, 2, 1);		/* TXD2 */
-	at91_set_a_periph(AT91_PIO_PORTD, 3, 0);		/* RXD2 */
-	writel(1 << AT91SAM9263_ID_US2, &pmc->pcer);
-}
-
-void at91_serial3_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTC, 30, 0);		/* DRXD */
-	at91_set_a_periph(AT91_PIO_PORTC, 31, 1);		/* DTXD */
-	writel(1 << AT91_ID_SYS, &pmc->pcer);
-}
-
-void at91_serial_hw_init(void)
-{
-#ifdef CONFIG_USART0
-	at91_serial0_hw_init();
-#endif
-
-#ifdef CONFIG_USART1
-	at91_serial1_hw_init();
-#endif
-
-#ifdef CONFIG_USART2
-	at91_serial2_hw_init();
-#endif
-
-#ifdef CONFIG_USART3	/* DBGU */
-	at91_serial3_hw_init();
-#endif
-}
-
-#ifdef CONFIG_HAS_DATAFLASH
-void at91_spi0_hw_init(unsigned long cs_mask)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_b_periph(AT91_PIO_PORTA, 0, 0);	/* SPI0_MISO */
-	at91_set_b_periph(AT91_PIO_PORTA, 1, 0);	/* SPI0_MOSI */
-	at91_set_b_periph(AT91_PIO_PORTA, 2, 0);	/* SPI0_SPCK */
-
-	/* Enable clock */
-	writel(1 << AT91SAM9263_ID_SPI0, &pmc->pcer);
-
-	if (cs_mask & (1 << 0)) {
-		at91_set_b_periph(AT91_PIO_PORTA, 5, 1);
-	}
-	if (cs_mask & (1 << 1)) {
-		at91_set_b_periph(AT91_PIO_PORTA, 3, 1);
-	}
-	if (cs_mask & (1 << 2)) {
-		at91_set_b_periph(AT91_PIO_PORTA, 4, 1);
-	}
-	if (cs_mask & (1 << 3)) {
-		at91_set_b_periph(AT91_PIO_PORTB, 11, 1);
-	}
-	if (cs_mask & (1 << 4)) {
-		at91_set_pio_output(AT91_PIO_PORTA, 5, 1);
-	}
-	if (cs_mask & (1 << 5)) {
-		at91_set_pio_output(AT91_PIO_PORTA, 3, 1);
-	}
-	if (cs_mask & (1 << 6)) {
-		at91_set_pio_output(AT91_PIO_PORTA, 4, 1);
-	}
-	if (cs_mask & (1 << 7)) {
-		at91_set_pio_output(AT91_PIO_PORTB, 11, 1);
-	}
-}
-
-void at91_spi1_hw_init(unsigned long cs_mask)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTB, 12, 0);	/* SPI1_MISO */
-	at91_set_a_periph(AT91_PIO_PORTB, 13, 0);	/* SPI1_MOSI */
-	at91_set_a_periph(AT91_PIO_PORTB, 14, 0);	/* SPI1_SPCK */
-
-	/* Enable clock */
-	writel(1 << AT91SAM9263_ID_SPI1, &pmc->pcer);
-
-	if (cs_mask & (1 << 0)) {
-		at91_set_a_periph(AT91_PIO_PORTB, 15, 1);
-	}
-	if (cs_mask & (1 << 1)) {
-		at91_set_a_periph(AT91_PIO_PORTB, 16, 1);
-	}
-	if (cs_mask & (1 << 2)) {
-		at91_set_a_periph(AT91_PIO_PORTB, 17, 1);
-	}
-	if (cs_mask & (1 << 3)) {
-		at91_set_a_periph(AT91_PIO_PORTB, 18, 1);
-	}
-	if (cs_mask & (1 << 4)) {
-		at91_set_pio_output(AT91_PIO_PORTB, 15, 1);
-	}
-	if (cs_mask & (1 << 5)) {
-		at91_set_pio_output(AT91_PIO_PORTB, 16, 1);
-	}
-	if (cs_mask & (1 << 6)) {
-		at91_set_pio_output(AT91_PIO_PORTB, 17, 1);
-	}
-	if (cs_mask & (1 << 7)) {
-		at91_set_pio_output(AT91_PIO_PORTB, 18, 1);
-	}
-}
-#endif
-
-#ifdef CONFIG_MACB
-void at91_macb_hw_init(void)
-{
-	at91_set_a_periph(AT91_PIO_PORTE, 21, 0);	/* ETXCK_EREFCK */
-	at91_set_b_periph(AT91_PIO_PORTC, 25, 0);	/* ERXDV */
-	at91_set_a_periph(AT91_PIO_PORTE, 25, 0);	/* ERX0 */
-	at91_set_a_periph(AT91_PIO_PORTE, 26, 0);	/* ERX1 */
-	at91_set_a_periph(AT91_PIO_PORTE, 27, 0);	/* ERXER */
-	at91_set_a_periph(AT91_PIO_PORTE, 28, 0);	/* ETXEN */
-	at91_set_a_periph(AT91_PIO_PORTE, 23, 0);	/* ETX0 */
-	at91_set_a_periph(AT91_PIO_PORTE, 24, 0);	/* ETX1 */
-	at91_set_a_periph(AT91_PIO_PORTE, 30, 0);	/* EMDIO */
-	at91_set_a_periph(AT91_PIO_PORTE, 29, 0);	/* EMDC */
-
-#ifndef CONFIG_RMII
-	at91_set_a_periph(AT91_PIO_PORTE, 22, 0);	/* ECRS */
-	at91_set_b_periph(AT91_PIO_PORTC, 26, 0);	/* ECOL */
-	at91_set_b_periph(AT91_PIO_PORTC, 22, 0);	/* ERX2 */
-	at91_set_b_periph(AT91_PIO_PORTC, 23, 0);	/* ERX3 */
-	at91_set_b_periph(AT91_PIO_PORTC, 27, 0);	/* ERXCK */
-	at91_set_b_periph(AT91_PIO_PORTC, 20, 0);	/* ETX2 */
-	at91_set_b_periph(AT91_PIO_PORTC, 21, 0);	/* ETX3 */
-	at91_set_b_periph(AT91_PIO_PORTC, 24, 0);	/* ETXER */
-#endif
-}
-#endif
-
-#ifdef CONFIG_USB_OHCI_NEW
-void at91_uhp_hw_init(void)
-{
-	/* Enable VBus on UHP ports */
-	at91_set_pio_output(AT91_PIO_PORTA, 21, 0);
-	at91_set_pio_output(AT91_PIO_PORTA, 24, 0);
-}
-#endif
-
-#ifdef CONFIG_AT91_CAN
-void at91_can_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTA, 13, 0);	/* CAN_TX */
-	at91_set_a_periph(AT91_PIO_PORTA, 14, 1);	/* CAN_RX */
-
-	/* Enable clock */
-	writel(1 << AT91SAM9263_ID_CAN, &pmc->pcer);
-}
-#endif
diff --git a/cpu/arm926ejs/at91/at91sam9m10g45_devices.c b/cpu/arm926ejs/at91/at91sam9m10g45_devices.c
deleted file mode 100644
index 4ad9b1fcc9..0000000000
--- a/cpu/arm926ejs/at91/at91sam9m10g45_devices.c
+++ /dev/null
@@ -1,187 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian.pop@leadtechdesign.com>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/io.h>
-
-void at91_serial0_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTB, 19, 1);	/* TXD0 */
-	at91_set_a_periph(AT91_PIO_PORTB, 18, 0);	/* RXD0 */
-	writel(1 << AT91SAM9G45_ID_US0, &pmc->pcer);
-}
-
-void at91_serial1_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTB, 4, 1);		/* TXD1 */
-	at91_set_a_periph(AT91_PIO_PORTB, 5, 0);		/* RXD1 */
-	writel(1 << AT91SAM9G45_ID_US1, &pmc->pcer);
-}
-
-void at91_serial2_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTD, 6, 1);		/* TXD2 */
-	at91_set_a_periph(AT91_PIO_PORTD, 7, 0);		/* RXD2 */
-	writel(1 << AT91SAM9G45_ID_US2, &pmc->pcer);
-}
-
-void at91_serial3_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTB, 12, 0);	/* DRXD */
-	at91_set_a_periph(AT91_PIO_PORTB, 13, 1);	/* DTXD */
-	writel(1 << AT91_ID_SYS, &pmc->pcer);
-}
-
-void at91_serial_hw_init(void)
-{
-#ifdef CONFIG_USART0
-	at91_serial0_hw_init();
-#endif
-
-#ifdef CONFIG_USART1
-	at91_serial1_hw_init();
-#endif
-
-#ifdef CONFIG_USART2
-	at91_serial2_hw_init();
-#endif
-
-#ifdef CONFIG_USART3	/* DBGU */
-	at91_serial3_hw_init();
-#endif
-}
-
-#ifdef CONFIG_ATMEL_SPI
-void at91_spi0_hw_init(unsigned long cs_mask)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTB, 0, 0);	/* SPI0_MISO */
-	at91_set_a_periph(AT91_PIO_PORTB, 1, 0);	/* SPI0_MOSI */
-	at91_set_a_periph(AT91_PIO_PORTB, 2, 0);	/* SPI0_SPCK */
-
-	/* Enable clock */
-	writel(1 << AT91SAM9G45_ID_SPI0, &pmc->pcer);
-
-	if (cs_mask & (1 << 0)) {
-		at91_set_a_periph(AT91_PIO_PORTB, 3, 0);
-	}
-	if (cs_mask & (1 << 1)) {
-		at91_set_b_periph(AT91_PIO_PORTB, 18, 0);
-	}
-	if (cs_mask & (1 << 2)) {
-		at91_set_b_periph(AT91_PIO_PORTB, 19, 0);
-	}
-	if (cs_mask & (1 << 3)) {
-		at91_set_b_periph(AT91_PIO_PORTD, 27, 0);
-	}
-	if (cs_mask & (1 << 4)) {
-		at91_set_pio_output(AT91_PIO_PORTB, 3, 0);
-	}
-	if (cs_mask & (1 << 5)) {
-		at91_set_pio_output(AT91_PIO_PORTB, 18, 0);
-	}
-	if (cs_mask & (1 << 6)) {
-		at91_set_pio_output(AT91_PIO_PORTB, 19, 0);
-	}
-	if (cs_mask & (1 << 7)) {
-		at91_set_pio_output(AT91_PIO_PORTD, 27, 0);
-	}
-}
-
-void at91_spi1_hw_init(unsigned long cs_mask)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTB, 14, 0);	/* SPI1_MISO */
-	at91_set_a_periph(AT91_PIO_PORTB, 15, 0);	/* SPI1_MOSI */
-	at91_set_a_periph(AT91_PIO_PORTB, 16, 0);	/* SPI1_SPCK */
-
-	/* Enable clock */
-	writel(1 << AT91SAM9G45_ID_SPI1, &pmc->pcer);
-
-	if (cs_mask & (1 << 0)) {
-		at91_set_a_periph(AT91_PIO_PORTB, 17, 0);
-	}
-	if (cs_mask & (1 << 1)) {
-		at91_set_b_periph(AT91_PIO_PORTD, 28, 0);
-	}
-	if (cs_mask & (1 << 2)) {
-		at91_set_a_periph(AT91_PIO_PORTD, 18, 0);
-	}
-	if (cs_mask & (1 << 3)) {
-		at91_set_a_periph(AT91_PIO_PORTD, 19, 0);
-	}
-	if (cs_mask & (1 << 4)) {
-		at91_set_pio_output(AT91_PIO_PORTB, 17, 0);
-	}
-	if (cs_mask & (1 << 5)) {
-		at91_set_pio_output(AT91_PIO_PORTD, 28, 0);
-	}
-	if (cs_mask & (1 << 6)) {
-		at91_set_pio_output(AT91_PIO_PORTD, 18, 0);
-	}
-	if (cs_mask & (1 << 7)) {
-		at91_set_pio_output(AT91_PIO_PORTD, 19, 0);
-	}
-
-}
-#endif
-
-#ifdef CONFIG_MACB
-void at91_macb_hw_init(void)
-{
-	at91_set_a_periph(AT91_PIO_PORTA, 17, 0);	/* ETXCK_EREFCK */
-	at91_set_a_periph(AT91_PIO_PORTA, 15, 0);	/* ERXDV */
-	at91_set_a_periph(AT91_PIO_PORTA, 12, 0);	/* ERX0 */
-	at91_set_a_periph(AT91_PIO_PORTA, 13, 0);	/* ERX1 */
-	at91_set_a_periph(AT91_PIO_PORTA, 16, 0);	/* ERXER */
-	at91_set_a_periph(AT91_PIO_PORTA, 14, 0);	/* ETXEN */
-	at91_set_a_periph(AT91_PIO_PORTA, 10, 0);	/* ETX0 */
-	at91_set_a_periph(AT91_PIO_PORTA, 11, 0);	/* ETX1 */
-	at91_set_a_periph(AT91_PIO_PORTA, 19, 0);	/* EMDIO */
-	at91_set_a_periph(AT91_PIO_PORTA, 18, 0);	/* EMDC */
-#ifndef CONFIG_RMII
-	at91_set_b_periph(AT91_PIO_PORTA, 29, 0);	/* ECRS */
-	at91_set_b_periph(AT91_PIO_PORTA, 30, 0);	/* ECOL */
-	at91_set_b_periph(AT91_PIO_PORTA, 8,  0);	/* ERX2 */
-	at91_set_b_periph(AT91_PIO_PORTA, 9,  0);	/* ERX3 */
-	at91_set_b_periph(AT91_PIO_PORTA, 28, 0);	/* ERXCK */
-	at91_set_b_periph(AT91_PIO_PORTA, 6,  0);	/* ETX2 */
-	at91_set_b_periph(AT91_PIO_PORTA, 7,  0);	/* ETX3 */
-	at91_set_b_periph(AT91_PIO_PORTA, 27, 0);	/* ETXER */
-#endif
-}
-#endif
diff --git a/cpu/arm926ejs/at91/at91sam9rl_devices.c b/cpu/arm926ejs/at91/at91sam9rl_devices.c
deleted file mode 100644
index 4f570f4fb5..0000000000
--- a/cpu/arm926ejs/at91/at91sam9rl_devices.c
+++ /dev/null
@@ -1,123 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian.pop@leadtechdesign.com>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/io.h>
-
-void at91_serial0_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTA, 6, 1);		/* TXD0 */
-	at91_set_a_periph(AT91_PIO_PORTA, 7, 0);		/* RXD0 */
-	writel(1 << AT91SAM9RL_ID_US0, &pmc->pcer);
-}
-
-void at91_serial1_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTA, 11, 1);		/* TXD1 */
-	at91_set_a_periph(AT91_PIO_PORTA, 12, 0);		/* RXD1 */
-	writel(1 << AT91SAM9RL_ID_US1, &pmc->pcer);
-}
-
-void at91_serial2_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTA, 13, 1);		/* TXD2 */
-	at91_set_a_periph(AT91_PIO_PORTA, 14, 0);		/* RXD2 */
-	writel(1 << AT91SAM9RL_ID_US2, &pmc->pcer);
-}
-
-void at91_serial3_hw_init(void)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTA, 21, 0);		/* DRXD */
-	at91_set_a_periph(AT91_PIO_PORTA, 22, 1);		/* DTXD */
-	writel(1 << AT91_ID_SYS, &pmc->pcer);
-}
-
-void at91_serial_hw_init(void)
-{
-#ifdef CONFIG_USART0
-	at91_serial0_hw_init();
-#endif
-
-#ifdef CONFIG_USART1
-	at91_serial1_hw_init();
-#endif
-
-#ifdef CONFIG_USART2
-	at91_serial2_hw_init();
-#endif
-
-#ifdef CONFIG_USART3	/* DBGU */
-	at91_serial3_hw_init();
-#endif
-}
-
-#ifdef CONFIG_HAS_DATAFLASH
-void at91_spi0_hw_init(unsigned long cs_mask)
-{
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
-
-	at91_set_a_periph(AT91_PIO_PORTA, 25, 0);	/* SPI0_MISO */
-	at91_set_a_periph(AT91_PIO_PORTA, 26, 0);	/* SPI0_MOSI */
-	at91_set_a_periph(AT91_PIO_PORTA, 27, 0);	/* SPI0_SPCK */
-
-	/* Enable clock */
-	writel(1 << AT91SAM9RL_ID_SPI, &pmc->pcer);
-
-	if (cs_mask & (1 << 0)) {
-		at91_set_a_periph(AT91_PIO_PORTA, 28, 1);
-	}
-	if (cs_mask & (1 << 1)) {
-		at91_set_b_periph(AT91_PIO_PORTB, 7, 1);
-	}
-	if (cs_mask & (1 << 2)) {
-		at91_set_a_periph(AT91_PIO_PORTD, 8, 1);
-	}
-	if (cs_mask & (1 << 3)) {
-		at91_set_b_periph(AT91_PIO_PORTD, 9, 1);
-	}
-	if (cs_mask & (1 << 4)) {
-		at91_set_pio_output(AT91_PIO_PORTA, 28, 1);
-	}
-	if (cs_mask & (1 << 5)) {
-		at91_set_pio_output(AT91_PIO_PORTB, 7, 1);
-	}
-	if (cs_mask & (1 << 6)) {
-		at91_set_pio_output(AT91_PIO_PORTD, 8, 1);
-	}
-	if (cs_mask & (1 << 7)) {
-		at91_set_pio_output(AT91_PIO_PORTD, 9, 1);
-	}
-}
-#endif
diff --git a/cpu/arm926ejs/at91/clock.c b/cpu/arm926ejs/at91/clock.c
deleted file mode 100644
index ecf91f5187..0000000000
--- a/cpu/arm926ejs/at91/clock.c
+++ /dev/null
@@ -1,216 +0,0 @@
-/*
- * [origin: Linux kernel linux/arch/arm/mach-at91/clock.c]
- *
- * Copyright (C) 2005 David Brownell
- * Copyright (C) 2005 Ivan Kokshaysky
- * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#include <config.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/io.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/clk.h>
-
-static unsigned long cpu_clk_rate_hz;
-static unsigned long main_clk_rate_hz;
-static unsigned long mck_rate_hz;
-static unsigned long plla_rate_hz;
-static unsigned long pllb_rate_hz;
-static u32 at91_pllb_usb_init;
-
-unsigned long get_cpu_clk_rate(void)
-{
-	return cpu_clk_rate_hz;
-}
-
-unsigned long get_main_clk_rate(void)
-{
-	return main_clk_rate_hz;
-}
-
-unsigned long get_mck_clk_rate(void)
-{
-	return mck_rate_hz;
-}
-
-unsigned long get_plla_clk_rate(void)
-{
-	return plla_rate_hz;
-}
-
-unsigned long get_pllb_clk_rate(void)
-{
-	return pllb_rate_hz;
-}
-
-u32 get_pllb_init(void)
-{
-	return at91_pllb_usb_init;
-}
-
-static unsigned long at91_css_to_rate(unsigned long css)
-{
-	switch (css) {
-	case AT91_PMC_MCKR_CSS_SLOW:
-		return AT91_SLOW_CLOCK;
-	case AT91_PMC_MCKR_CSS_MAIN:
-		return main_clk_rate_hz;
-	case AT91_PMC_MCKR_CSS_PLLA:
-		return plla_rate_hz;
-	case AT91_PMC_MCKR_CSS_PLLB:
-		return pllb_rate_hz;
-	}
-
-	return 0;
-}
-
-#ifdef CONFIG_USB_ATMEL
-static unsigned at91_pll_calc(unsigned main_freq, unsigned out_freq)
-{
-	unsigned i, div = 0, mul = 0, diff = 1 << 30;
-	unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
-
-	/* PLL output max 240 MHz (or 180 MHz per errata) */
-	if (out_freq > 240000000)
-		goto fail;
-
-	for (i = 1; i < 256; i++) {
-		int diff1;
-		unsigned input, mul1;
-
-		/*
-		 * PLL input between 1MHz and 32MHz per spec, but lower
-		 * frequences seem necessary in some cases so allow 100K.
-		 * Warning: some newer products need 2MHz min.
-		 */
-		input = main_freq / i;
-#if defined(CONFIG_AT91SAM9G20)
-		if (input < 2000000)
-			continue;
-#endif
-		if (input < 100000)
-			continue;
-		if (input > 32000000)
-			continue;
-
-		mul1 = out_freq / input;
-#if defined(CONFIG_AT91SAM9G20)
-		if (mul > 63)
-			continue;
-#endif
-		if (mul1 > 2048)
-			continue;
-		if (mul1 < 2)
-			goto fail;
-
-		diff1 = out_freq - input * mul1;
-		if (diff1 < 0)
-			diff1 = -diff1;
-		if (diff > diff1) {
-			diff = diff1;
-			div = i;
-			mul = mul1;
-			if (diff == 0)
-				break;
-		}
-	}
-	if (i == 256 && diff > (out_freq >> 5))
-		goto fail;
-	return ret | ((mul - 1) << 16) | div;
-fail:
-	return 0;
-}
-#endif
-
-static u32 at91_pll_rate(u32 freq, u32 reg)
-{
-	unsigned mul, div;
-
-	div = reg & 0xff;
-	mul = (reg >> 16) & 0x7ff;
-	if (div && mul) {
-		freq /= div;
-		freq *= mul + 1;
-	} else
-		freq = 0;
-
-	return freq;
-}
-
-int at91_clock_init(unsigned long main_clock)
-{
-	unsigned freq, mckr;
-	at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
-#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
-	unsigned tmp;
-	/*
-	 * When the bootloader initialized the main oscillator correctly,
-	 * there's no problem using the cycle counter.  But if it didn't,
-	 * or when using oscillator bypass mode, we must be told the speed
-	 * of the main clock.
-	 */
-	if (!main_clock) {
-		do {
-			tmp = readl(&pmc->mcfr);
-		} while (!(tmp & AT91_PMC_MCFR_MAINRDY));
-		tmp &= AT91_PMC_MCFR_MAINF_MASK;
-		main_clock = tmp * (AT91_SLOW_CLOCK / 16);
-	}
-#endif
-	main_clk_rate_hz = main_clock;
-
-	/* report if PLLA is more than mildly overclocked */
-	plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
-
-#ifdef CONFIG_USB_ATMEL
-	/*
-	 * USB clock init:  choose 48 MHz PLLB value,
-	 * disable 48MHz clock during usb peripheral suspend.
-	 *
-	 * REVISIT:  assumes MCK doesn't derive from PLLB!
-	 */
-	at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
-			     AT91_PMC_PLLBR_USBDIV_2;
-	pllb_rate_hz = at91_pll_rate(main_clock, at91_pllb_usb_init);
-#endif
-
-	/*
-	 * MCK and CPU derive from one of those primary clocks.
-	 * For now, assume this parentage won't change.
-	 */
-	mckr = readl(&pmc->mckr);
-#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
-	/* plla divisor by 2 */
-	plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12));
-#endif
-	mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
-	freq = mck_rate_hz;
-
-	freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2));	/* prescale */
-#if defined(CONFIG_AT91RM9200)
-	/* mdiv */
-	mck_rate_hz = freq / (1 + ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
-#elif defined(CONFIG_AT91SAM9G20)
-	/* mdiv ; (x >> 7) = ((x >> 8) * 2) */
-	mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ?
-		freq / ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 7) : freq;
-	if (mckr & AT91_PMC_MCKR_MDIV_MASK)
-		freq /= 2;			/* processor clock division */
-#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
-	mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ==
-		(AT91_PMC_MCKR_MDIV_2 | AT91_PMC_MCKR_MDIV_4)
-		? freq / 3
-		: freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
-#else
-	mck_rate_hz = freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
-#endif
-	cpu_clk_rate_hz = freq;
-
-	return 0;
-}
diff --git a/cpu/arm926ejs/at91/config.mk b/cpu/arm926ejs/at91/config.mk
deleted file mode 100644
index 19296fdba2..0000000000
--- a/cpu/arm926ejs/at91/config.mk
+++ /dev/null
@@ -1 +0,0 @@
-PLATFORM_CPPFLAGS += $(call cc-option,-mtune=arm926ejs,)
diff --git a/cpu/arm926ejs/at91/cpu.c b/cpu/arm926ejs/at91/cpu.c
deleted file mode 100644
index 141a7d1ec6..0000000000
--- a/cpu/arm926ejs/at91/cpu.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * (C) Copyright 2009
- * Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#ifdef CONFIG_AT91_LEGACY
-#warning Your board is using legacy SoC access. Please update!
-#endif
-
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/io.h>
-
-#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
-#define CONFIG_SYS_AT91_MAIN_CLOCK 0
-#endif
-
-/*
- * The at91sam9260 has 4 GPBR (0-3), we'll use the last one, nr 3,
- * to keep track of the bootcount.
- */
-#define AT91_GPBR_BOOTCOUNT_REGISTER 3
-#define AT91_BOOTCOUNT_ADDRESS (AT91_GPBR + 4*AT91_GPBR_BOOTCOUNT_REGISTER)
-
-int arch_cpu_init(void)
-{
-	return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
-}
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo(void)
-{
-	char buf[32];
-
-	printf("CPU: %s\n", CONFIG_SYS_AT91_CPU_NAME);
-	printf("Crystal frequency: %8s MHz\n",
-					strmhz(buf, get_main_clk_rate()));
-	printf("CPU clock        : %8s MHz\n",
-					strmhz(buf, get_cpu_clk_rate()));
-	printf("Master clock     : %8s MHz\n",
-					strmhz(buf, get_mck_clk_rate()));
-
-	return 0;
-}
-#endif
-
-#ifdef CONFIG_BOOTCOUNT_LIMIT
-/*
- * Just as the mpc5xxx, we combine the BOOTCOUNT_MAGIC and boocount
- * in one 32-bit register. This is done, as the AT91SAM9260 only has
- * 4 GPBR.
- */
-void bootcount_store (ulong a)
-{
-	volatile ulong *save_addr =
-		(volatile ulong *)(AT91_BASE_SYS + AT91_BOOTCOUNT_ADDRESS);
-
-	*save_addr = (BOOTCOUNT_MAGIC & 0xffff0000) | (a & 0x0000ffff);
-}
-
-ulong bootcount_load (void)
-{
-	volatile ulong *save_addr =
-		(volatile ulong *)(AT91_BASE_SYS + AT91_BOOTCOUNT_ADDRESS);
-
-	if ((*save_addr & 0xffff0000) != (BOOTCOUNT_MAGIC & 0xffff0000))
-		return 0;
-	else
-		return (*save_addr & 0x0000ffff);
-}
-
-#endif /* CONFIG_BOOTCOUNT_LIMIT */
diff --git a/cpu/arm926ejs/at91/led.c b/cpu/arm926ejs/at91/led.c
deleted file mode 100644
index 0a315c4971..0000000000
--- a/cpu/arm926ejs/at91/led.c
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian.pop@leadtechdesign.com>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_pio.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/io.h>
-
-#ifdef CONFIG_RED_LED
-void red_LED_on(void)
-{
-	at91_set_gpio_value(CONFIG_RED_LED, 1);
-}
-
-void red_LED_off(void)
-{
-	at91_set_gpio_value(CONFIG_RED_LED, 0);
-}
-#endif
-
-#ifdef CONFIG_GREEN_LED
-void green_LED_on(void)
-{
-	at91_set_gpio_value(CONFIG_GREEN_LED, 0);
-}
-
-void green_LED_off(void)
-{
-	at91_set_gpio_value(CONFIG_GREEN_LED, 1);
-}
-#endif
-
-#ifdef CONFIG_YELLOW_LED
-void yellow_LED_on(void)
-{
-	at91_set_gpio_value(CONFIG_YELLOW_LED, 0);
-}
-
-void yellow_LED_off(void)
-{
-	at91_set_gpio_value(CONFIG_YELLOW_LED, 1);
-}
-#endif
diff --git a/cpu/arm926ejs/at91/lowlevel_init.S b/cpu/arm926ejs/at91/lowlevel_init.S
deleted file mode 100644
index 559c35c9ee..0000000000
--- a/cpu/arm926ejs/at91/lowlevel_init.S
+++ /dev/null
@@ -1,274 +0,0 @@
-/*
- * Memory Setup stuff - taken from blob memsetup.S
- *
- * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
- *		       Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
- *
- * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
- * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_wdt.h>
-#include <asm/arch/at91_pio.h>
-#include <asm/arch/at91_matrix.h>
-#include <asm/arch/at91sam9_sdramc.h>
-#include <asm/arch/at91sam9_smc.h>
-#include <asm/arch/at91_rstc.h>
-#ifdef CONFIG_AT91_LEGACY
-#include <asm/arch/at91sam9_matrix.h>
-#endif
-#ifndef CONFIG_SYS_MATRIX_EBICSA_VAL
-#define CONFIG_SYS_MATRIX_EBICSA_VAL CONFIG_SYS_MATRIX_EBI0CSA_VAL
-#endif
-
-_TEXT_BASE:
-	.word	TEXT_BASE
-
-.globl lowlevel_init
-.type lowlevel_init,function
-lowlevel_init:
-
-	mov	r5, pc		/* r5 = POS1 + 4 current */
-POS1:
-	ldr	r0, =POS1	/* r0 = POS1 compile */
-	ldr	r2, _TEXT_BASE
-	sub	r0, r0, r2	/* r0 = POS1-_TEXT_BASE (POS1 relative) */
-	sub	r5, r5, r0	/* r0 = TEXT_BASE-1 */
-	sub	r5, r5, #4	/* r1 = text base - current */
-
-	/* memory control configuration 1 */
-	ldr	r0, =SMRDATA
-	ldr	r2, =SMRDATA1
-	ldr	r1, _TEXT_BASE
-	sub	r0, r0, r1
-	sub	r2, r2, r1
-	add	r0, r0, r5
-	add	r2, r2, r5
-0:
-	/* the address */
-	ldr	r1, [r0], #4
-	/* the value */
-	ldr	r3, [r0], #4
-	str	r3, [r1]
-	cmp	r2, r0
-	bne	0b
-
-/* ----------------------------------------------------------------------------
- * PMC Init Step 1.
- * ----------------------------------------------------------------------------
- * - Check if the PLL is already initialized
- * ----------------------------------------------------------------------------
- */
-	ldr	r1, =(AT91_ASM_PMC_MCKR)
-	ldr	r0, [r1]
-	and	r0, r0, #3
-	cmp	r0, #0
-	bne	PLL_setup_end
-
-/* ---------------------------------------------------------------------------
- * - Enable the Main Oscillator
- * ---------------------------------------------------------------------------
- */
-	ldr	r1, =(AT91_ASM_PMC_MOR)
-	ldr	r2, =(AT91_ASM_PMC_SR)
-	/* Main oscillator Enable register PMC_MOR: */
-	ldr	r0, =CONFIG_SYS_MOR_VAL
-	str	r0, [r1]
-
-	/* Reading the PMC Status to detect when the Main Oscillator is enabled */
-	mov	r4, #AT91_PMC_IXR_MOSCS
-MOSCS_Loop:
-	ldr	r3, [r2]
-	and	r3, r4, r3
-	cmp	r3, #AT91_PMC_IXR_MOSCS
-	bne	MOSCS_Loop
-
-/* ----------------------------------------------------------------------------
- * PMC Init Step 2.
- * ----------------------------------------------------------------------------
- * Setup PLLA
- * ----------------------------------------------------------------------------
- */
-	ldr	r1, =(AT91_ASM_PMC_PLLAR)
-	ldr	r0, =CONFIG_SYS_PLLAR_VAL
-	str	r0, [r1]
-
-	/* Reading the PMC Status register to detect when the PLLA is locked */
-	mov	r4, #AT91_PMC_IXR_LOCKA
-MOSCS_Loop1:
-	ldr	r3, [r2]
-	and	r3, r4, r3
-	cmp	r3, #AT91_PMC_IXR_LOCKA
-	bne	MOSCS_Loop1
-
-/* ----------------------------------------------------------------------------
- * PMC Init Step 3.
- * ----------------------------------------------------------------------------
- * - Switch on the Main Oscillator
- * ----------------------------------------------------------------------------
- */
-	ldr	r1, =(AT91_ASM_PMC_MCKR)
-
-	/* -Master Clock Controller register PMC_MCKR */
-	ldr	r0, =CONFIG_SYS_MCKR1_VAL
-	str	r0, [r1]
-
-	/* Reading the PMC Status to detect when the Master clock is ready */
-	mov	r4, #AT91_PMC_IXR_MCKRDY
-MCKRDY_Loop:
-	ldr	r3, [r2]
-	and	r3, r4, r3
-	cmp	r3, #AT91_PMC_IXR_MCKRDY
-	bne	MCKRDY_Loop
-
-	ldr	r0, =CONFIG_SYS_MCKR2_VAL
-	str	r0, [r1]
-
-	/* Reading the PMC Status to detect when the Master clock is ready */
-	mov	r4, #AT91_PMC_IXR_MCKRDY
-MCKRDY_Loop1:
-	ldr	r3, [r2]
-	and	r3, r4, r3
-	cmp	r3, #AT91_PMC_IXR_MCKRDY
-	bne	MCKRDY_Loop1
-PLL_setup_end:
-
-/* ----------------------------------------------------------------------------
- * - memory control configuration 2
- * ----------------------------------------------------------------------------
- */
-	ldr	r0, =(AT91_ASM_SDRAMC_TR)
-	ldr	r1, [r0]
-	cmp	r1, #0
-	bne	SDRAM_setup_end
-
-	ldr	r0, =SMRDATA1
-	ldr	r2, =SMRDATA2
-	ldr	r1, _TEXT_BASE
-	sub	r0, r0, r1
-	sub	r2, r2, r1
-	add	r0, r0, r5
-	add	r2, r2, r5
-2:
-	/* the address */
-	ldr	r1, [r0], #4
-	/* the value */
-	ldr	r3, [r0], #4
-	str	r3, [r1]
-	cmp	r2, r0
-	bne	2b
-
-SDRAM_setup_end:
-	/* everything is fine now */
-	mov	pc, lr
-
-	.ltorg
-
-SMRDATA:
-	.word AT91_ASM_WDT_MR
-	.word CONFIG_SYS_WDTC_WDMR_VAL
-	/* configure PIOx as EBI0 D[16-31] */
-#if defined(CONFIG_AT91SAM9263)
-	.word AT91_ASM_PIOD_PDR
-	.word CONFIG_SYS_PIOD_PDR_VAL1
-	.word AT91_ASM_PIOD_PUDR
-	.word CONFIG_SYS_PIOD_PPUDR_VAL
-	.word AT91_ASM_PIOD_ASR
-	.word CONFIG_SYS_PIOD_PPUDR_VAL
-#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) \
-	|| defined(CONFIG_AT91SAM9G20)
-	.word AT91_ASM_PIOC_PDR
-	.word CONFIG_SYS_PIOC_PDR_VAL1
-	.word AT91_ASM_PIOC_PUDR
-	.word CONFIG_SYS_PIOC_PPUDR_VAL
-#endif
-	.word AT91_ASM_MATRIX_CSA0
-	.word CONFIG_SYS_MATRIX_EBICSA_VAL
-
-	/* flash */
-	.word AT91_ASM_SMC_MODE0
-	.word CONFIG_SYS_SMC0_MODE0_VAL
-
-	.word AT91_ASM_SMC_CYCLE0
-	.word CONFIG_SYS_SMC0_CYCLE0_VAL
-
-	.word AT91_ASM_SMC_PULSE0
-	.word CONFIG_SYS_SMC0_PULSE0_VAL
-
-	.word AT91_ASM_SMC_SETUP0
-	.word CONFIG_SYS_SMC0_SETUP0_VAL
-
-SMRDATA1:
-	.word AT91_ASM_SDRAMC_MR
-	.word CONFIG_SYS_SDRC_MR_VAL1
-	.word AT91_ASM_SDRAMC_TR
-	.word CONFIG_SYS_SDRC_TR_VAL1
-	.word AT91_ASM_SDRAMC_CR
-	.word CONFIG_SYS_SDRC_CR_VAL
-	.word AT91_ASM_SDRAMC_MDR
-	.word CONFIG_SYS_SDRC_MDR_VAL
-	.word AT91_ASM_SDRAMC_MR
-	.word CONFIG_SYS_SDRC_MR_VAL2
-	.word AT91_SDRAM_BASE
-	.word CONFIG_SYS_SDRAM_VAL1
-	.word AT91_ASM_SDRAMC_MR
-	.word CONFIG_SYS_SDRC_MR_VAL3
-	.word AT91_SDRAM_BASE
-	.word CONFIG_SYS_SDRAM_VAL2
-	.word AT91_SDRAM_BASE
-	.word CONFIG_SYS_SDRAM_VAL3
-	.word AT91_SDRAM_BASE
-	.word CONFIG_SYS_SDRAM_VAL4
-	.word AT91_SDRAM_BASE
-	.word CONFIG_SYS_SDRAM_VAL5
-	.word AT91_SDRAM_BASE
-	.word CONFIG_SYS_SDRAM_VAL6
-	.word AT91_SDRAM_BASE
-	.word CONFIG_SYS_SDRAM_VAL7
-	.word AT91_SDRAM_BASE
-	.word CONFIG_SYS_SDRAM_VAL8
-	.word AT91_SDRAM_BASE
-	.word CONFIG_SYS_SDRAM_VAL9
-	.word AT91_ASM_SDRAMC_MR
-	.word CONFIG_SYS_SDRC_MR_VAL4
-	.word AT91_SDRAM_BASE
-	.word CONFIG_SYS_SDRAM_VAL10
-	.word AT91_ASM_SDRAMC_MR
-	.word CONFIG_SYS_SDRC_MR_VAL5
-	.word AT91_SDRAM_BASE
-	.word CONFIG_SYS_SDRAM_VAL11
-	.word AT91_ASM_SDRAMC_TR
-	.word CONFIG_SYS_SDRC_TR_VAL2
-	.word AT91_SDRAM_BASE
-	.word CONFIG_SYS_SDRAM_VAL12
-	/* User reset enable*/
-	.word AT91_ASM_RSTC_MR
-	.word CONFIG_SYS_RSTC_RMR_VAL
-#ifdef CONFIG_SYS_MATRIX_MCFG_REMAP
-	/* MATRIX_MCFG - REMAP all masters */
-	.word AT91_ASM_MATRIX_MCFG
-	.word 0x1FF
-#endif
-SMRDATA2:
-	.word 0
diff --git a/cpu/arm926ejs/at91/reset.c b/cpu/arm926ejs/at91/reset.c
deleted file mode 100644
index 1b67e77887..0000000000
--- a/cpu/arm926ejs/at91/reset.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian.pop@leadtechdesign.com>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_rstc.h>
-#include <asm/arch/io.h>
-
-/*
- * Reset the cpu by setting up the watchdog timer and let him time out.
- */
-void reset_cpu(ulong ignored)
-{
-	at91_rstc_t *rstc = (at91_rstc_t *) AT91_RSTC_BASE;
-
-	/* this is the way Linux does it */
-
-	writel(AT91_RSTC_KEY | AT91_RSTC_CR_PROCRST | AT91_RSTC_CR_PERRST,
-		&rstc->cr);
-
-	while (1);
-	/* Never reached */
-}
diff --git a/cpu/arm926ejs/at91/timer.c b/cpu/arm926ejs/at91/timer.c
deleted file mode 100644
index d21eebfb4e..0000000000
--- a/cpu/arm926ejs/at91/timer.c
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian.pop@leadtechdesign.com>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_pit.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/io.h>
-#include <div64.h>
-
-/*
- * We're using the AT91CAP9/SAM9 PITC in 32 bit mode, by
- * setting the 20 bit counter period to its maximum (0xfffff).
- */
-#define TIMER_LOAD_VAL	0xfffff
-
-static ulong timestamp;
-static ulong lastinc;
-static ulong timer_freq;
-
-static inline unsigned long long tick_to_time(unsigned long long tick)
-{
-	tick *= CONFIG_SYS_HZ;
-	do_div(tick, timer_freq);
-
-	return tick;
-}
-
-static inline unsigned long long usec_to_tick(unsigned long long usec)
-{
-	usec *= timer_freq;
-	do_div(usec, 1000000);
-
-	return usec;
-}
-
-/* nothing really to do with interrupts, just starts up a counter. */
-int timer_init(void)
-{
-	at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
-	at91_pit_t *pit = (at91_pit_t *) AT91_PIT_BASE;
-	/*
-	 * Enable PITC Clock
-	 * The clock is already enabled for system controller in boot
-	 */
-	writel(1 << AT91_ID_SYS, &pmc->pcer);
-
-	/* Enable PITC */
-	writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);
-
-	reset_timer_masked();
-
-	timer_freq = get_mck_clk_rate() >> 4;
-
-	return 0;
-}
-
-/*
- * timer without interrupts
- */
-unsigned long long get_ticks(void)
-{
-	at91_pit_t *pit = (at91_pit_t *) AT91_PIT_BASE;
-
-	ulong now = readl(&pit->piir);
-
-	if (now >= lastinc)	/* normal mode (non roll) */
-		/* move stamp forward with absolut diff ticks */
-		timestamp += (now - lastinc);
-	else			/* we have rollover of incrementer */
-		timestamp += (0xFFFFFFFF - lastinc) + now;
-	lastinc = now;
-	return timestamp;
-}
-
-void reset_timer_masked(void)
-{
-	/* reset time */
-	at91_pit_t *pit = (at91_pit_t *) AT91_PIT_BASE;
-
-	/* capture current incrementer value time */
-	lastinc = readl(&pit->piir);
-	timestamp = 0; /* start "advancing" time stamp from 0 */
-}
-
-ulong get_timer_masked(void)
-{
-	return tick_to_time(get_ticks());
-}
-
-void __udelay(unsigned long usec)
-{
-	unsigned long long tmp;
-	ulong tmo;
-
-	tmo = usec_to_tick(usec);
-	tmp = get_ticks() + tmo;	/* get current timestamp */
-
-	while (get_ticks() < tmp)	/* loop till event */
-		 /*NOP*/;
-}
-
-void reset_timer(void)
-{
-	reset_timer_masked();
-}
-
-ulong get_timer(ulong base)
-{
-	return get_timer_masked () - base;
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
-	ulong tbclk;
-
-	tbclk = CONFIG_SYS_HZ;
-	return tbclk;
-}
diff --git a/cpu/arm926ejs/config.mk b/cpu/arm926ejs/config.mk
deleted file mode 100644
index f8ef90f2d5..0000000000
--- a/cpu/arm926ejs/config.mk
+++ /dev/null
@@ -1,32 +0,0 @@
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
-
-PLATFORM_CPPFLAGS += -march=armv5te
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# =========================================================================
-PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
diff --git a/cpu/arm926ejs/cpu.c b/cpu/arm926ejs/cpu.c
deleted file mode 100644
index 5c902dfc13..0000000000
--- a/cpu/arm926ejs/cpu.c
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * CPU specific code
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/system.h>
-
-static void cache_flush(void);
-
-int cleanup_before_linux (void)
-{
-	/*
-	 * this function is called just before we call linux
-	 * it prepares the processor for linux
-	 *
-	 * we turn off caches etc ...
-	 */
-
-	disable_interrupts ();
-
-
-	/* turn off I/D-cache */
-	icache_disable();
-	dcache_disable();
-	/* flush I/D-cache */
-	cache_flush();
-
-	return 0;
-}
-
-/* flush I/D-cache */
-static void cache_flush (void)
-{
-	unsigned long i = 0;
-
-	asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));
-}
diff --git a/cpu/arm926ejs/davinci/Makefile b/cpu/arm926ejs/davinci/Makefile
deleted file mode 100644
index d7e9e2ca04..0000000000
--- a/cpu/arm926ejs/davinci/Makefile
+++ /dev/null
@@ -1,59 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).a
-
-COBJS-y				+= cpu.o timer.o psc.o
-COBJS-$(CONFIG_SOC_DM355)	+= dm355.o
-COBJS-$(CONFIG_SOC_DM365)	+= dm365.o
-COBJS-$(CONFIG_SOC_DM644X)	+= dm644x.o
-COBJS-$(CONFIG_SOC_DM646X)	+= dm646x.o
-COBJS-$(CONFIG_DRIVER_TI_EMAC)	+= lxt972.o dp83848.o
-
-SOBJS	= reset.o
-
-ifndef CONFIG_SKIP_LOWLEVEL_INIT
-SOBJS	+= lowlevel_init.o
-endif
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y) $(SOBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS)
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/cpu/arm926ejs/davinci/config.mk b/cpu/arm926ejs/davinci/config.mk
deleted file mode 100644
index 565adda11d..0000000000
--- a/cpu/arm926ejs/davinci/config.mk
+++ /dev/null
@@ -1,32 +0,0 @@
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
-
-PLATFORM_CPPFLAGS += -march=armv5te
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# =========================================================================
-PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
diff --git a/cpu/arm926ejs/davinci/cpu.c b/cpu/arm926ejs/davinci/cpu.c
deleted file mode 100644
index fc3551c302..0000000000
--- a/cpu/arm926ejs/davinci/cpu.c
+++ /dev/null
@@ -1,191 +0,0 @@
-/*
- * Copyright (C) 2004 Texas Instruments.
- * Copyright (C) 2009 David Brownell
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/arch/hardware.h>
-#include <asm/io.h>
-
-/* offsets from PLL controller base */
-#define PLLC_PLLCTL	0x100
-#define PLLC_PLLM	0x110
-#define PLLC_PREDIV	0x114
-#define PLLC_PLLDIV1	0x118
-#define PLLC_PLLDIV2	0x11c
-#define PLLC_PLLDIV3	0x120
-#define PLLC_POSTDIV	0x128
-#define PLLC_BPDIV	0x12c
-#define PLLC_PLLDIV4	0x160
-#define PLLC_PLLDIV5	0x164
-#define PLLC_PLLDIV6	0x168
-#define PLLC_PLLDIV8	0x170
-#define PLLC_PLLDIV9	0x174
-
-#define BIT(x)		(1 << (x))
-
-/* SOC-specific pll info */
-#ifdef CONFIG_SOC_DM355
-#define ARM_PLLDIV	PLLC_PLLDIV1
-#define DDR_PLLDIV	PLLC_PLLDIV1
-#endif
-
-#ifdef CONFIG_SOC_DM644X
-#define ARM_PLLDIV	PLLC_PLLDIV2
-#define DSP_PLLDIV	PLLC_PLLDIV1
-#define DDR_PLLDIV	PLLC_PLLDIV2
-#endif
-
-#ifdef CONFIG_SOC_DM6447
-#define ARM_PLLDIV	PLLC_PLLDIV2
-#define DSP_PLLDIV	PLLC_PLLDIV1
-#define DDR_PLLDIV	PLLC_PLLDIV1
-#endif
-
-#ifdef CONFIG_SOC_DA8XX
-const dv_reg * const sysdiv[7] = {
-	&davinci_pllc_regs->plldiv1, &davinci_pllc_regs->plldiv2,
-	&davinci_pllc_regs->plldiv3, &davinci_pllc_regs->plldiv4,
-	&davinci_pllc_regs->plldiv5, &davinci_pllc_regs->plldiv6,
-	&davinci_pllc_regs->plldiv7
-};
-
-int clk_get(enum davinci_clk_ids id)
-{
-	int pre_div;
-	int pllm;
-	int post_div;
-	int pll_out;
-
-	pll_out = CONFIG_SYS_OSCIN_FREQ;
-
-	if (id == DAVINCI_AUXCLK_CLKID)
-		goto out;
-
-	/*
-	 * Lets keep this simple. Combining operations can result in
-	 * unexpected approximations
-	 */
-	pre_div = (readl(&davinci_pllc_regs->prediv) &
-		   DAVINCI_PLLC_DIV_MASK) + 1;
-	pllm = readl(&davinci_pllc_regs->pllm) + 1;
-
-	pll_out /= pre_div;
-	pll_out *= pllm;
-
-	if (id == DAVINCI_PLLM_CLKID)
-		goto out;
-
-	post_div = (readl(&davinci_pllc_regs->postdiv) &
-		    DAVINCI_PLLC_DIV_MASK) + 1;
-
-	pll_out /= post_div;
-
-	if (id == DAVINCI_PLLC_CLKID)
-		goto out;
-
-	pll_out /= (readl(sysdiv[id - 1]) & DAVINCI_PLLC_DIV_MASK) + 1;
-
-out:
-	return pll_out;
-}
-#endif /* CONFIG_SOC_DA8XX */
-
-#ifdef CONFIG_DISPLAY_CPUINFO
-
-static unsigned pll_div(volatile void *pllbase, unsigned offset)
-{
-	u32	div;
-
-	div = REG(pllbase + offset);
-	return (div & BIT(15)) ? (1 + (div & 0x1f)) : 1;
-}
-
-static inline unsigned pll_prediv(volatile void *pllbase)
-{
-#ifdef CONFIG_SOC_DM355
-	/* this register read seems to fail on pll0 */
-	if (pllbase == (volatile void *)DAVINCI_PLL_CNTRL0_BASE)
-		return 8;
-	else
-		return pll_div(pllbase, PLLC_PREDIV);
-#endif
-	return 1;
-}
-
-static inline unsigned pll_postdiv(volatile void *pllbase)
-{
-#ifdef CONFIG_SOC_DM355
-	return pll_div(pllbase, PLLC_POSTDIV);
-#elif defined(CONFIG_SOC_DM6446)
-	if (pllbase == (volatile void *)DAVINCI_PLL_CNTRL0_BASE)
-		return pll_div(pllbase, PLLC_POSTDIV);
-#endif
-	return 1;
-}
-
-static unsigned pll_sysclk_mhz(unsigned pll_addr, unsigned div)
-{
-	volatile void	*pllbase = (volatile void *) pll_addr;
-	unsigned	base = CONFIG_SYS_HZ_CLOCK / 1000;
-
-	/* the PLL might be bypassed */
-	if (REG(pllbase + PLLC_PLLCTL) & BIT(0)) {
-		base /= pll_prediv(pllbase);
-		base *= 1 + (REG(pllbase + PLLC_PLLM) & 0x0ff);
-		base /= pll_postdiv(pllbase);
-	}
-	return DIV_ROUND_UP(base, 1000 * pll_div(pllbase, div));
-}
-
-int print_cpuinfo(void)
-{
-	/* REVISIT fetch and display CPU ID and revision information
-	 * too ... that will matter as more revisions appear.
-	 */
-	printf("Cores: ARM %d MHz",
-			pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV));
-
-#ifdef DSP_PLLDIV
-	printf(", DSP %d MHz",
-			pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DSP_PLLDIV));
-#endif
-
-	printf("\nDDR:   %d MHz\n",
-			/* DDR PHY uses an x2 input clock */
-			pll_sysclk_mhz(DAVINCI_PLL_CNTRL1_BASE, DDR_PLLDIV)
-				/ 2);
-	return 0;
-}
-
-#endif
-
-/*
- * Initializes on-chip ethernet controllers.
- * to override, implement board_eth_init()
- */
-int cpu_eth_init(bd_t *bis)
-{
-#if defined(CONFIG_DRIVER_TI_EMAC)
-	davinci_emac_initialize();
-#endif
-	return 0;
-}
diff --git a/cpu/arm926ejs/davinci/dm355.c b/cpu/arm926ejs/davinci/dm355.c
deleted file mode 100644
index bc45b67fbe..0000000000
--- a/cpu/arm926ejs/davinci/dm355.c
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * SoC-specific code for tms320dm355 and similar chips
- *
- * Copyright (C) 2009 David Brownell
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-
-
-void davinci_enable_uart0(void)
-{
-	lpsc_on(DAVINCI_LPSC_UART0);
-
-	/* Bringup UART0 out of reset */
-	REG(UART0_PWREMU_MGMT) = 0x00006001;
-}
-
-
-#ifdef CONFIG_DRIVER_DAVINCI_I2C
-void davinci_enable_i2c(void)
-{
-	lpsc_on(DAVINCI_LPSC_I2C);
-
-	/* Enable I2C pin Mux */
-	REG(PINMUX3) |= (1 << 20) | (1 << 19);
-}
-#endif
diff --git a/cpu/arm926ejs/davinci/dm365.c b/cpu/arm926ejs/davinci/dm365.c
deleted file mode 100644
index 56c1bc032b..0000000000
--- a/cpu/arm926ejs/davinci/dm365.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * SoC-specific code for tms320dm365 and similar chips
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-
-void davinci_enable_uart0(void)
-{
-	lpsc_on(DAVINCI_LPSC_UART0);
-}
-
-#ifdef CONFIG_DRIVER_DAVINCI_I2C
-void davinci_enable_i2c(void)
-{
-	lpsc_on(DAVINCI_LPSC_I2C);
-}
-#endif
diff --git a/cpu/arm926ejs/davinci/dm644x.c b/cpu/arm926ejs/davinci/dm644x.c
deleted file mode 100644
index bb105b56ee..0000000000
--- a/cpu/arm926ejs/davinci/dm644x.c
+++ /dev/null
@@ -1,96 +0,0 @@
-/*
- * SoC-specific code for tms320dm644x chips
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
- * Copyright (C) 2004 Texas Instruments.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-
-
-#define PINMUX0_EMACEN (1 << 31)
-#define PINMUX0_AECS5  (1 << 11)
-#define PINMUX0_AECS4  (1 << 10)
-
-#define PINMUX1_I2C    (1 <<  7)
-#define PINMUX1_UART1  (1 <<  1)
-#define PINMUX1_UART0  (1 <<  0)
-
-
-void davinci_enable_uart0(void)
-{
-	lpsc_on(DAVINCI_LPSC_UART0);
-
-	/* Bringup UART0 out of reset */
-	REG(UART0_PWREMU_MGMT) = 0x00006001;
-
-	/* Enable UART0 MUX lines */
-	REG(PINMUX1) |= PINMUX1_UART0;
-}
-
-#ifdef CONFIG_DRIVER_TI_EMAC
-void davinci_enable_emac(void)
-{
-	lpsc_on(DAVINCI_LPSC_EMAC);
-	lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER);
-	lpsc_on(DAVINCI_LPSC_MDIO);
-
-	/* Enable GIO3.3V cells used for EMAC */
-	REG(VDD3P3V_PWDN) = 0;
-
-	/* Enable EMAC. */
-	REG(PINMUX0) |= PINMUX0_EMACEN;
-}
-#endif
-
-#ifdef CONFIG_DRIVER_DAVINCI_I2C
-void davinci_enable_i2c(void)
-{
-	lpsc_on(DAVINCI_LPSC_I2C);
-
-	/* Enable I2C pin Mux */
-	REG(PINMUX1) |= PINMUX1_I2C;
-}
-#endif
-
-void davinci_errata_workarounds(void)
-{
-	/*
-	 * Workaround for TMS320DM6446 errata 1.3.22:
-	 *   PSC: PTSTAT Register Does Not Clear After Warm/Maximum Reset
-	 *   Revision(s) Affected: 1.3 and earlier
-	 */
-	REG(PSC_SILVER_BULLET) = 0;
-
-	/*
-	 * Set the PR_OLD_COUNT bits in the Bus Burst Priority Register (PBBPR)
-	 * as suggested in TMS320DM6446 errata 2.1.2:
-	 *
-	 * On DM6446 Silicon Revision 2.1 and earlier, under certain conditions
-	 * low priority modules can occupy the bus and prevent high priority
-	 * modules like the VPSS from getting the required DDR2 throughput.
-	 * A hex value of 0x20 should provide a good ARM (cache enabled)
-	 * performance and still allow good utilization by the VPSS or other
-	 * modules.
-	 */
-	REG(VBPR) = 0x20;
-}
diff --git a/cpu/arm926ejs/davinci/dm646x.c b/cpu/arm926ejs/davinci/dm646x.c
deleted file mode 100644
index 329825f453..0000000000
--- a/cpu/arm926ejs/davinci/dm646x.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * SoC-specific code for TMS320DM646x chips
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <asm/arch/hardware.h>
-
-void davinci_enable_uart0(void)
-{
-	lpsc_on(DAVINCI_DM646X_LPSC_UART0);
-}
-
-#ifdef CONFIG_DRIVER_TI_EMAC
-void davinci_enable_emac(void)
-{
-	lpsc_on(DAVINCI_DM646X_LPSC_EMAC);
-}
-#endif
-
-#ifdef CONFIG_DRIVER_DAVINCI_I2C
-void davinci_enable_i2c(void)
-{
-	lpsc_on(DAVINCI_DM646X_LPSC_I2C);
-}
-#endif
diff --git a/cpu/arm926ejs/davinci/dp83848.c b/cpu/arm926ejs/davinci/dp83848.c
deleted file mode 100644
index c71c685f72..0000000000
--- a/cpu/arm926ejs/davinci/dp83848.c
+++ /dev/null
@@ -1,143 +0,0 @@
-/*
- * National Semiconductor DP83848 PHY Driver for TI DaVinci
- * (TMS320DM644x) based boards.
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * --------------------------------------------------------
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <net.h>
-#include <dp83848.h>
-#include <asm/arch/emac_defs.h>
-
-#ifdef CONFIG_DRIVER_TI_EMAC
-
-#ifdef CONFIG_CMD_NET
-
-int dp83848_is_phy_connected(int phy_addr)
-{
-	u_int16_t	id1, id2;
-
-	if (!davinci_eth_phy_read(phy_addr, DP83848_PHYID1_REG, &id1))
-		return(0);
-	if (!davinci_eth_phy_read(phy_addr, DP83848_PHYID2_REG, &id2))
-		return(0);
-
-	if ((id1 == DP83848_PHYID1_OUI) && (id2 == DP83848_PHYID2_OUI))
-		return(1);
-
-	return(0);
-}
-
-int dp83848_get_link_speed(int phy_addr)
-{
-	u_int16_t		tmp;
-	volatile emac_regs*	emac = (emac_regs *)EMAC_BASE_ADDR;
-
-	if (!davinci_eth_phy_read(phy_addr, DP83848_STAT_REG, &tmp))
-		return(0);
-
-	if (!(tmp & DP83848_LINK_STATUS))	/* link up? */
-		return(0);
-
-	if (!davinci_eth_phy_read(phy_addr, DP83848_PHY_STAT_REG, &tmp))
-		return(0);
-
-	/* Speed doesn't matter, there is no setting for it in EMAC... */
-	if (tmp & DP83848_DUPLEX) {
-		/* set DM644x EMAC for Full Duplex  */
-		emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE |
-			EMAC_MACCONTROL_FULLDUPLEX_ENABLE;
-	} else {
-		/*set DM644x EMAC for Half Duplex  */
-		emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE;
-	}
-
-	return(1);
-}
-
-
-int dp83848_init_phy(int phy_addr)
-{
-	int	ret = 1;
-
-	if (!dp83848_get_link_speed(phy_addr)) {
-		/* Try another time */
-		udelay(100000);
-		ret = dp83848_get_link_speed(phy_addr);
-	}
-
-	/* Disable PHY Interrupts */
-	davinci_eth_phy_write(phy_addr, DP83848_PHY_INTR_CTRL_REG, 0);
-
-	return(ret);
-}
-
-
-int dp83848_auto_negotiate(int phy_addr)
-{
-	u_int16_t	tmp;
-
-
-	if (!davinci_eth_phy_read(phy_addr, DP83848_CTL_REG, &tmp))
-		return(0);
-
-	/* Restart Auto_negotiation  */
-	tmp &= ~DP83848_AUTONEG;	/* remove autonegotiation enable */
-	tmp |= DP83848_ISOLATE;		/* Electrically isolate PHY */
-	davinci_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp);
-
-	/* Set the Auto_negotiation Advertisement Register
-	 * MII advertising for Next page, 100BaseTxFD and HD,
-	 * 10BaseTFD and HD, IEEE 802.3
-	 */
-	tmp = DP83848_NP | DP83848_TX_FDX | DP83848_TX_HDX |
-		DP83848_10_FDX | DP83848_10_HDX | DP83848_AN_IEEE_802_3;
-	davinci_eth_phy_write(phy_addr, DP83848_ANA_REG, tmp);
-
-
-	/* Read Control Register */
-	if (!davinci_eth_phy_read(phy_addr, DP83848_CTL_REG, &tmp))
-		return(0);
-
-	tmp |= DP83848_SPEED_SELECT | DP83848_AUTONEG | DP83848_DUPLEX_MODE;
-	davinci_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp);
-
-	/* Restart Auto_negotiation  */
-	tmp |= DP83848_RESTART_AUTONEG;
-	davinci_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp);
-
-	/*check AutoNegotiate complete */
-	udelay(10000);
-	if (!davinci_eth_phy_read(phy_addr, DP83848_STAT_REG, &tmp))
-		return(0);
-
-	if (!(tmp & DP83848_AUTONEG_COMP))
-		return(0);
-
-	return (dp83848_get_link_speed(phy_addr));
-}
-
-#endif	/* CONFIG_CMD_NET */
-
-#endif	/* CONFIG_DRIVER_ETHER */
diff --git a/cpu/arm926ejs/davinci/lowlevel_init.S b/cpu/arm926ejs/davinci/lowlevel_init.S
deleted file mode 100644
index 0a4b2cf674..0000000000
--- a/cpu/arm926ejs/davinci/lowlevel_init.S
+++ /dev/null
@@ -1,707 +0,0 @@
-/*
- * Low-level board setup code for TI DaVinci SoC based boards.
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * Partially based on TI sources, original copyrights follow:
- */
-
-/*
- * Board specific setup info
- *
- * (C) Copyright 2003
- * Texas Instruments, <www.ti.com>
- * Kshitij Gupta <Kshitij@ti.com>
- *
- * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
- *
- * Modified for OMAP 5912 OSK board by Rishi Bhattacharya, Apr 2004
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * Modified for DV-EVM board by Rishi Bhattacharya, Apr 2005
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * Modified for DV-EVM board by Swaminathan S, Nov 2005
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-
-.globl	lowlevel_init
-lowlevel_init:
-
-	/*-------------------------------------------------------*
-	 * Mask all IRQs by setting all bits in the EINT default *
-	 *-------------------------------------------------------*/
-	mov	r1, $0
-	ldr	r0, =EINT_ENABLE0
-	str	r1, [r0]
-	ldr	r0, =EINT_ENABLE1
-	str	r1, [r0]
-
-	/*------------------------------------------------------*
-	 * Put the GEM in reset					*
-	 *------------------------------------------------------*/
-
-	/* Put the GEM in reset */
-	ldr	r8, PSC_GEM_FLAG_CLEAR
-	ldr	r6, MDCTL_GEM
-	ldr	r7, [r6]
-	and	r7, r7, r8
-	str	r7, [r6]
-
-	/* Enable the Power Domain Transition Command */
-	ldr	r6, PTCMD
-	ldr	r7, [r6]
-	orr	r7, r7, $0x02
-	str	r7, [r6]
-
-	/* Check for Transition Complete(PTSTAT) */
-checkStatClkStopGem:
-	ldr	r6, PTSTAT
-	ldr	r7, [r6]
-	ands	r7, r7, $0x02
-	bne	checkStatClkStopGem
-
-	/* Check for GEM Reset Completion */
-checkGemStatClkStop:
-	ldr	r6, MDSTAT_GEM
-	ldr	r7, [r6]
-	ands	r7, r7, $0x100
-	bne	checkGemStatClkStop
-
-	/* Do this for enabling a WDT initiated reset this is a workaround
-	   for a chip bug.  Not required under normal situations */
-	ldr	r6, P1394
-	mov	r10, $0
-	str	r10, [r6]
-
-	/*------------------------------------------------------*
-	 * Enable L1 & L2 Memories in Fast mode                 *
-	 *------------------------------------------------------*/
-	ldr	r6, DFT_ENABLE
-	mov	r10, $0x01
-	str	r10, [r6]
-
-	ldr	r6, MMARG_BRF0
-	ldr	r10, MMARG_BRF0_VAL
-	str	r10, [r6]
-
-	ldr	r6, DFT_ENABLE
-	mov	r10, $0
-	str	r10, [r6]
-
-	/*------------------------------------------------------*
-	 * DDR2 PLL Initialization				*
-	 *------------------------------------------------------*/
-
-	/* Select the Clock Mode Depending on the Value written in the Boot Table by the run script */
-	mov	r10, $0
-	ldr	r6, PLL2_CTL
-	ldr	r7, PLL_CLKSRC_MASK
-	ldr	r8, [r6]
-	and	r8, r8, r7
-	mov	r9, r10, lsl $8
-	orr	r8, r8, r9
-	str	r8, [r6]
-
-	/* Select the PLLEN source */
-	ldr	r7, PLL_ENSRC_MASK
-	and	r8, r8, r7
-	str	r8, [r6]
-
-	/* Bypass the PLL */
-	ldr	r7, PLL_BYPASS_MASK
-	and	r8, r8, r7
-	str	r8, [r6]
-
-	/* Wait for few cycles to allow PLLEN Mux switch properly to bypass Clock */
-	mov	r10, $0x20
-WaitPPL2Loop:
-	subs	r10, r10, $1
-	bne	WaitPPL2Loop
-
-	/* Reset the PLL */
-	ldr	r7, PLL_RESET_MASK
-	and	r8, r8, r7
-	str	r8, [r6]
-
-	/* Power up the PLL */
-	ldr	r7, PLL_PWRUP_MASK
-	and	r8, r8, r7
-	str	r8, [r6]
-
-	/* Enable the PLL from Disable Mode */
-	ldr	r7, PLL_DISABLE_ENABLE_MASK
-	and	r8, r8, r7
-	str	r8, [r6]
-
-	/* Program the PLL Multiplier */
-	ldr	r6, PLL2_PLLM
-	mov	r2, $0x17	/* 162 MHz */
-	str	r2, [r6]
-
-	/* Program the PLL2 Divisor Value */
-	ldr	r6, PLL2_DIV2
-	mov	r3, $0x01
-	str	r3, [r6]
-
-	/* Program the PLL2 Divisor Value */
-	ldr	r6, PLL2_DIV1
-	mov	r4, $0x0b	/* 54 MHz */
-	str	r4, [r6]
-
-	/* PLL2 DIV2 MMR */
-	ldr	r8, PLL2_DIV_MASK
-	ldr	r6, PLL2_DIV2
-	ldr	r9, [r6]
-	and	r8, r8, r9
-	mov	r9, $0x01
-	mov	r9, r9, lsl $15
-	orr	r8, r8, r9
-	str	r8, [r6]
-
-	/* Program the GOSET bit to take new divider values */
-	ldr	r6, PLL2_PLLCMD
-	ldr	r7, [r6]
-	orr	r7, r7, $0x01
-	str	r7, [r6]
-
-	/* Wait for Done */
-	ldr	r6, PLL2_PLLSTAT
-doneLoop_0:
-	ldr	r7, [r6]
-	ands	r7, r7, $0x01
-	bne	doneLoop_0
-
-	/* PLL2 DIV1 MMR */
-	ldr	r8, PLL2_DIV_MASK
-	ldr	r6, PLL2_DIV1
-	ldr	r9, [r6]
-	and	r8, r8, r9
-	mov	r9, $0x01
-	mov	r9, r9, lsl $15
-	orr	r8, r8, r9
-	str	r8, [r6]
-
-	/* Program the GOSET bit to take new divider values */
-	ldr	r6, PLL2_PLLCMD
-	ldr	r7, [r6]
-	orr	r7, r7, $0x01
-	str	r7, [r6]
-
-	/* Wait for Done */
-	ldr	r6, PLL2_PLLSTAT
-doneLoop:
-	ldr	r7, [r6]
-	ands	r7, r7, $0x01
-	bne	doneLoop
-
-	/* Wait for PLL to Reset Properly */
-	mov	r10, $0x218
-ResetPPL2Loop:
-	subs	r10, r10, $1
-	bne	ResetPPL2Loop
-
-	/* Bring PLL out of Reset */
-	ldr	r6, PLL2_CTL
-	ldr	r8, [r6]
-	orr	r8, r8, $0x08
-	str	r8, [r6]
-
-	/* Wait for PLL to Lock */
-	ldr	r10, PLL_LOCK_COUNT
-PLL2Lock:
-	subs	r10, r10, $1
-	bne	PLL2Lock
-
-	/* Enable the PLL */
-	ldr	r6, PLL2_CTL
-	ldr	r8, [r6]
-	orr	r8, r8, $0x01
-	str	r8, [r6]
-
-	/*------------------------------------------------------*
-	 * Issue Soft Reset to DDR Module			*
-	 *------------------------------------------------------*/
-
-	/* Shut down the DDR2 LPSC Module */
-	ldr	r8, PSC_FLAG_CLEAR
-	ldr	r6, MDCTL_DDR2
-	ldr	r7, [r6]
-	and	r7, r7, r8
-	orr	r7, r7, $0x03
-	str	r7, [r6]
-
-	/* Enable the Power Domain Transition Command */
-	ldr	r6, PTCMD
-	ldr	r7, [r6]
-	orr	r7, r7, $0x01
-	str	r7, [r6]
-
-	/* Check for Transition Complete(PTSTAT) */
-checkStatClkStop:
-	ldr	r6, PTSTAT
-	ldr	r7, [r6]
-	ands	r7, r7, $0x01
-	bne	checkStatClkStop
-
-	/* Check for DDR2 Controller Enable Completion */
-checkDDRStatClkStop:
-	ldr	r6, MDSTAT_DDR2
-	ldr	r7, [r6]
-	and	r7, r7, $0x1f
-	cmp	r7, $0x03
-	bne	checkDDRStatClkStop
-
-	/*------------------------------------------------------*
-	 * Program DDR2 MMRs for 162MHz Setting			*
-	 *------------------------------------------------------*/
-
-	/* Program PHY Control Register */
-	ldr	r6, DDRCTL
-	ldr	r7, DDRCTL_VAL
-	str	r7, [r6]
-
-	/* Program SDRAM Bank Config Register */
-	ldr	r6, SDCFG
-	ldr	r7, SDCFG_VAL
-	str	r7, [r6]
-
-	/* Program SDRAM TIM-0 Config Register */
-	ldr	r6, SDTIM0
-	ldr	r7, SDTIM0_VAL_162MHz
-	str	r7, [r6]
-
-	/* Program SDRAM TIM-1 Config Register */
-	ldr	r6, SDTIM1
-	ldr	r7, SDTIM1_VAL_162MHz
-	str	r7, [r6]
-
-	/* Program the SDRAM Bank Config Control Register */
-	ldr	r10, MASK_VAL
-	ldr	r8, SDCFG
-	ldr	r9, SDCFG_VAL
-	and	r9, r9, r10
-	str	r9, [r8]
-
-	/* Program SDRAM SDREF Config Register */
-	ldr	r6, SDREF
-	ldr	r7, SDREF_VAL
-	str	r7, [r6]
-
-	/*------------------------------------------------------*
-	 * Issue Soft Reset to DDR Module			*
-	 *------------------------------------------------------*/
-
-	/* Issue a Dummy DDR2 read/write */
-	ldr	r8, DDR2_START_ADDR
-	ldr	r7, DUMMY_VAL
-	str	r7, [r8]
-	ldr	r7, [r8]
-
-	/* Shut down the DDR2 LPSC Module */
-	ldr	r8, PSC_FLAG_CLEAR
-	ldr	r6, MDCTL_DDR2
-	ldr	r7, [r6]
-	and	r7, r7, r8
-	orr	r7, r7, $0x01
-	str	r7, [r6]
-
-	/* Enable the Power Domain Transition Command */
-	ldr	r6, PTCMD
-	ldr	r7, [r6]
-	orr	r7, r7, $0x01
-	str	r7, [r6]
-
-	/* Check for Transition Complete(PTSTAT) */
-checkStatClkStop2:
-	ldr	r6, PTSTAT
-	ldr	r7, [r6]
-	ands	r7, r7, $0x01
-	bne	checkStatClkStop2
-
-	/* Check for DDR2 Controller Enable Completion */
-checkDDRStatClkStop2:
-	ldr	r6, MDSTAT_DDR2
-	ldr	r7, [r6]
-	and	r7, r7, $0x1f
-	cmp	r7, $0x01
-	bne	checkDDRStatClkStop2
-
-	/*------------------------------------------------------*
-	 * Turn DDR2 Controller Clocks On			*
-	 *------------------------------------------------------*/
-
-	/* Enable the DDR2 LPSC Module */
-	ldr	r6, MDCTL_DDR2
-	ldr	r7, [r6]
-	orr	r7, r7, $0x03
-	str	r7, [r6]
-
-	/* Enable the Power Domain Transition Command */
-	ldr	r6, PTCMD
-	ldr	r7, [r6]
-	orr	r7, r7, $0x01
-	str	r7, [r6]
-
-	/* Check for Transition Complete(PTSTAT) */
-checkStatClkEn2:
-	ldr	r6, PTSTAT
-	ldr	r7, [r6]
-	ands	r7, r7, $0x01
-	bne	checkStatClkEn2
-
-	/* Check for DDR2 Controller Enable Completion */
-checkDDRStatClkEn2:
-	ldr	r6, MDSTAT_DDR2
-	ldr	r7, [r6]
-	and	r7, r7, $0x1f
-	cmp	r7, $0x03
-	bne	checkDDRStatClkEn2
-
-	/*  DDR Writes and Reads */
-	ldr	r6, CFGTEST
-	mov	r3, $0x01
-	str	r3, [r6]
-
-	/*------------------------------------------------------*
-	 * System PLL Initialization				*
-	 *------------------------------------------------------*/
-
-	/* Select the Clock Mode Depending on the Value written in the Boot Table by the run script */
-	mov	r2, $0
-	ldr	r6, PLL1_CTL
-	ldr	r7, PLL_CLKSRC_MASK
-	ldr	r8, [r6]
-	and	r8, r8, r7
-	mov	r9, r2, lsl $8
-	orr	r8, r8, r9
-	str	r8, [r6]
-
-	/* Select the PLLEN source */
-	ldr	r7, PLL_ENSRC_MASK
-	and	r8, r8, r7
-	str	r8, [r6]
-
-	/* Bypass the PLL */
-	ldr	r7, PLL_BYPASS_MASK
-	and	r8, r8, r7
-	str	r8, [r6]
-
-	/* Wait for few cycles to allow PLLEN Mux switch properly to bypass Clock */
-	mov	r10, $0x20
-
-WaitLoop:
-	subs	r10, r10, $1
-	bne	WaitLoop
-
-	/* Reset the PLL */
-	ldr	r7, PLL_RESET_MASK
-	and	r8, r8, r7
-	str	r8, [r6]
-
-	/* Disable the PLL */
-	orr	r8, r8, $0x10
-	str	r8, [r6]
-
-	/* Power up the PLL */
-	ldr	r7, PLL_PWRUP_MASK
-	and	r8, r8, r7
-	str	r8, [r6]
-
-	/* Enable the PLL from Disable Mode */
-	ldr	r7, PLL_DISABLE_ENABLE_MASK
-	and	r8, r8, r7
-	str	r8, [r6]
-
-	/* Program the PLL Multiplier */
-	ldr	r6, PLL1_PLLM
-	mov	r3, $0x15	/* For 594MHz */
-	str	r3, [r6]
-
-	/* Wait for PLL to Reset Properly */
-	mov	r10, $0xff
-
-ResetLoop:
-	subs	r10, r10, $1
-	bne	ResetLoop
-
-	/* Bring PLL out of Reset */
-	ldr	r6, PLL1_CTL
-	orr	r8, r8, $0x08
-	str	r8, [r6]
-
-	/* Wait for PLL to Lock */
-	ldr	r10, PLL_LOCK_COUNT
-
-PLL1Lock:
-	subs	r10, r10, $1
-	bne	PLL1Lock
-
-	/* Enable the PLL */
-	orr	r8, r8, $0x01
-	str	r8, [r6]
-
-	nop
-	nop
-	nop
-	nop
-
-	/*------------------------------------------------------*
-	 * AEMIF configuration for NOR Flash (double check)     *
-	 *------------------------------------------------------*/
-	ldr	r0, _PINMUX0
-	ldr	r1, _DEV_SETTING
-	str	r1, [r0]
-
-	ldr	r0, WAITCFG
-	ldr	r1, WAITCFG_VAL
-	ldr	r2, [r0]
-	orr	r2, r2, r1
-	str	r2, [r0]
-
-	ldr	r0, ACFG3
-	ldr	r1, ACFG3_VAL
-	ldr	r2, [r0]
-	and	r1, r2, r1
-	str	r1, [r0]
-
-	ldr	r0, ACFG4
-	ldr	r1, ACFG4_VAL
-	ldr	r2, [r0]
-	and	r1, r2, r1
-	str	r1, [r0]
-
-	ldr	r0, ACFG5
-	ldr	r1, ACFG5_VAL
-	ldr	r2, [r0]
-	and	r1, r2, r1
-	str	r1, [r0]
-
-	/*--------------------------------------*
-	 * VTP manual Calibration               *
-	 *--------------------------------------*/
-	ldr	r0, VTPIOCR
-	ldr	r1, VTP_MMR0
-	str	r1, [r0]
-
-	ldr	r0, VTPIOCR
-	ldr	r1, VTP_MMR1
-	str	r1, [r0]
-
-	/* Wait for 33 VTP CLK cycles.  VRP operates at 27 MHz */
-	ldr	r10, VTP_LOCK_COUNT
-VTPLock:
-	subs	r10, r10, $1
-	bne	VTPLock
-
-	ldr	r6, DFT_ENABLE
-	mov	r10, $0x01
-	str	r10, [r6]
-
-	ldr	r6, DDRVTPR
-	ldr	r7, [r6]
-	and	r7, r7, $0x1f
-	and	r8, r7, $0x3e0
-	orr	r8, r7, r8
-	ldr	r7, VTP_RECAL
-	orr	r8, r7, r8
-	ldr	r7, VTP_EN
-	orr	r8, r7, r8
-	str	r8, [r0]
-
-
-	/* Wait for 33 VTP CLK cycles.  VRP operates at 27 MHz */
-	ldr	r10, VTP_LOCK_COUNT
-VTP1Lock:
-	subs	r10, r10, $1
-	bne	VTP1Lock
-
-	ldr	r1, [r0]
-	ldr	r2, VTP_MASK
-	and	r2, r1, r2
-	str	r2, [r0]
-
-	ldr	r6, DFT_ENABLE
-	mov	r10, $0
-	str	r10, [r6]
-
-	/*
-	 * Call board-specific lowlevel init.
-	 * That MUST be present and THAT returns
-	 * back to arch calling code with "mov pc, lr."
-	 */
-	b	dv_board_init
-
-.ltorg
-
-_PINMUX0:
-	.word	0x01c40000		/* Device Configuration Registers */
-_PINMUX1:
-	.word	0x01c40004		/* Device Configuration Registers */
-
-_DEV_SETTING:
-	.word	0x00000c1f
-
-WAITCFG:
-	.word	0x01e00004
-WAITCFG_VAL:
-	.word	0
-ACFG3:
-	.word	0x01e00014
-ACFG3_VAL:
-	.word	0x3ffffffd
-ACFG4:
-	.word	0x01e00018
-ACFG4_VAL:
-	.word	0x3ffffffd
-ACFG5:
-	.word	0x01e0001c
-ACFG5_VAL:
-	.word	0x3ffffffd
-
-MDCTL_DDR2:
-	.word	0x01c41a34
-MDSTAT_DDR2:
-	.word	0x01c41834
-
-PTCMD:
-	.word	0x01c41120
-PTSTAT:
-	.word	0x01c41128
-
-EINT_ENABLE0:
-	.word	0x01c48018
-EINT_ENABLE1:
-	.word	0x01c4801c
-
-PSC_FLAG_CLEAR:
-	.word	0xffffffe0
-PSC_GEM_FLAG_CLEAR:
-	.word	0xfffffeff
-
-/* DDR2 MMR & CONFIGURATION VALUES, 162 MHZ clock */
-DDRCTL:
-	.word	0x200000e4
-DDRCTL_VAL:
-	.word	0x50006405
-SDREF:
-	.word	0x2000000c
-SDREF_VAL:
-	.word	0x000005c3
-SDCFG:
-	.word	0x20000008
-SDCFG_VAL:
-#ifdef	DDR_4BANKS
-	.word	0x00178622
-#elif defined DDR_8BANKS
-	.word	0x00178632
-#else
-#error "Unknown DDR configuration!!!"
-#endif
-SDTIM0:
-	.word	0x20000010
-SDTIM0_VAL_162MHz:
-	.word	0x28923211
-SDTIM1:
-	.word	0x20000014
-SDTIM1_VAL_162MHz:
-	.word	0x0016c722
-VTPIOCR:
-	.word	0x200000f0	/* VTP IO Control register */
-DDRVTPR:
-	.word	0x01c42030	/* DDR VPTR MMR */
-VTP_MMR0:
-	.word	0x201f
-VTP_MMR1:
-	.word	0xa01f
-DFT_ENABLE:
-	.word	0x01c4004c
-VTP_LOCK_COUNT:
-	.word	0x5b0
-VTP_MASK:
-	.word	0xffffdfff
-VTP_RECAL:
-	.word	0x40000
-VTP_EN:
-	.word	0x02000
-CFGTEST:
-	.word	0x80010000
-MASK_VAL:
-	.word	0x00000fff
-
-/* GEM Power Up & LPSC Control Register */
-MDCTL_GEM:
-	.word	0x01c41a9c
-MDSTAT_GEM:
-	.word	0x01c4189c
-
-/* For WDT reset chip bug */
-P1394:
-	.word	0x01c41a20
-
-PLL_CLKSRC_MASK:
-	.word	0xfffffeff	/* Mask the Clock Mode bit */
-PLL_ENSRC_MASK:
-	.word	0xffffffdf	/* Select the PLLEN source */
-PLL_BYPASS_MASK:
-	.word	0xfffffffe	/* Put the PLL in BYPASS */
-PLL_RESET_MASK:
-	.word	0xfffffff7	/* Put the PLL in Reset Mode */
-PLL_PWRUP_MASK:
-	.word	0xfffffffd	/* PLL Power up Mask Bit  */
-PLL_DISABLE_ENABLE_MASK:
-	.word	0xffffffef	/* Enable the PLL from Disable */
-PLL_LOCK_COUNT:
-	.word	0x2000
-
-/* PLL1-SYSTEM PLL MMRs */
-PLL1_CTL:
-	.word	0x01c40900
-PLL1_PLLM:
-	.word	0x01c40910
-
-/* PLL2-SYSTEM PLL MMRs */
-PLL2_CTL:
-	.word	0x01c40d00
-PLL2_PLLM:
-	.word	0x01c40d10
-PLL2_DIV1:
-	.word	0x01c40d18
-PLL2_DIV2:
-	.word	0x01c40d1c
-PLL2_PLLCMD:
-	.word	0x01c40d38
-PLL2_PLLSTAT:
-	.word	0x01c40d3c
-PLL2_DIV_MASK:
-	.word	0xffff7fff
-
-MMARG_BRF0:
-	.word	0x01c42010	/* BRF margin mode 0 (R/W)*/
-MMARG_BRF0_VAL:
-	.word	0x00444400
-
-DDR2_START_ADDR:
-	.word	0x80000000
-DUMMY_VAL:
-	.word	0xa55aa55a
diff --git a/cpu/arm926ejs/davinci/lxt972.c b/cpu/arm926ejs/davinci/lxt972.c
deleted file mode 100644
index ce3e41c551..0000000000
--- a/cpu/arm926ejs/davinci/lxt972.c
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
- * Intel LXT971/LXT972 PHY Driver for TI DaVinci
- * (TMS320DM644x) based boards.
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * --------------------------------------------------------
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <net.h>
-#include <miiphy.h>
-#include <lxt971a.h>
-#include <asm/arch/emac_defs.h>
-
-#ifdef CONFIG_DRIVER_TI_EMAC
-
-#ifdef CONFIG_CMD_NET
-
-int lxt972_is_phy_connected(int phy_addr)
-{
-	u_int16_t id1, id2;
-
-	if (!davinci_eth_phy_read(phy_addr, PHY_PHYIDR1, &id1))
-		return(0);
-	if (!davinci_eth_phy_read(phy_addr, PHY_PHYIDR2, &id2))
-		return(0);
-
-	if ((id1 == (0x0013)) && ((id2  & 0xfff0) == 0x78e0))
-		return(1);
-
-	return(0);
-}
-
-int lxt972_get_link_speed(int phy_addr)
-{
-	u_int16_t stat1, tmp;
-	volatile emac_regs *emac = (emac_regs *)EMAC_BASE_ADDR;
-
-	if (!davinci_eth_phy_read(phy_addr, PHY_LXT971_STAT2, &stat1))
-		return(0);
-
-	if (!(stat1 & PHY_LXT971_STAT2_LINK))	/* link up? */
-		return(0);
-
-	if (!davinci_eth_phy_read(phy_addr, PHY_LXT971_DIG_CFG, &tmp))
-		return(0);
-
-	tmp |= PHY_LXT971_DIG_CFG_MII_DRIVE;
-
-	davinci_eth_phy_write(phy_addr, PHY_LXT971_DIG_CFG, tmp);
-	/* Read back */
-	if (!davinci_eth_phy_read(phy_addr, PHY_LXT971_DIG_CFG, &tmp))
-		return(0);
-
-	/* Speed doesn't matter, there is no setting for it in EMAC... */
-	if (stat1 & PHY_LXT971_STAT2_DUPLEX_MODE) {
-		/* set DM644x EMAC for Full Duplex  */
-		emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE |
-			EMAC_MACCONTROL_FULLDUPLEX_ENABLE;
-	} else {
-		/*set DM644x EMAC for Half Duplex  */
-		emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE;
-	}
-
-	return(1);
-}
-
-
-int lxt972_init_phy(int phy_addr)
-{
-	int ret = 1;
-
-	if (!lxt972_get_link_speed(phy_addr)) {
-		/* Try another time */
-		ret = lxt972_get_link_speed(phy_addr);
-	}
-
-	/* Disable PHY Interrupts */
-	davinci_eth_phy_write(phy_addr, PHY_LXT971_INT_ENABLE, 0);
-
-	return(ret);
-}
-
-
-int lxt972_auto_negotiate(int phy_addr)
-{
-	u_int16_t tmp;
-
-	if (!davinci_eth_phy_read(phy_addr, PHY_BMCR, &tmp))
-		return(0);
-
-	/* Restart Auto_negotiation  */
-	tmp |= PHY_BMCR_RST_NEG;
-	davinci_eth_phy_write(phy_addr, PHY_BMCR, tmp);
-
-	/*check AutoNegotiate complete */
-	udelay (10000);
-	if (!davinci_eth_phy_read(phy_addr, PHY_BMSR, &tmp))
-		return(0);
-
-	if (!(tmp & PHY_BMSR_AUTN_COMP))
-		return(0);
-
-	return (lxt972_get_link_speed(phy_addr));
-}
-
-#endif	/* CONFIG_CMD_NET */
-
-#endif	/* CONFIG_DRIVER_ETHER */
diff --git a/cpu/arm926ejs/davinci/psc.c b/cpu/arm926ejs/davinci/psc.c
deleted file mode 100644
index 8273a7fae4..0000000000
--- a/cpu/arm926ejs/davinci/psc.c
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- * Power and Sleep Controller (PSC) functions.
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
- * Copyright (C) 2004 Texas Instruments.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-#include <asm/io.h>
-
-/*
- * The PSC manages three inputs to a "module" which may be a peripheral or
- * CPU.  Those inputs are the module's:  clock; reset signal; and sometimes
- * its power domain.  For our purposes, we only care whether clock and power
- * are active, and the module is out of reset.
- *
- * DaVinci chips may include two separate power domains: "Always On" and "DSP".
- * Chips without a DSP generally have only one domain.
- *
- * The "Always On" power domain is always on when the chip is on, and is
- * powered by the VDD pins (on DM644X). The majority of DaVinci modules
- * lie within the "Always On" power domain.
- *
- * A separate domain called the "DSP" domain houses the C64x+ and other video
- * hardware such as VICP. In some chips, the "DSP" domain is not always on.
- * The "DSP" power domain is powered by the CVDDDSP pins (on DM644X).
- */
-
-/* Works on Always On power domain only (no PD argument) */
-void lpsc_on(unsigned int id)
-{
-	dv_reg_p mdstat, mdctl, ptstat, ptcmd;
-#ifdef CONFIG_SOC_DA8XX
-	struct davinci_psc_regs *psc_regs;
-#endif
-
-#ifndef CONFIG_SOC_DA8XX
-	if (id >= DAVINCI_LPSC_GEM)
-		return;			/* Don't work on DSP Power Domain */
-
-	mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4));
-	mdctl = REG_P(PSC_MDCTL_BASE + (id * 4));
-	ptstat = REG_P(PSC_PTSTAT);
-	ptcmd = REG_P(PSC_PTCMD);
-#else
-	if (id < DAVINCI_LPSC_PSC1_BASE) {
-		if (id >= PSC_PSC0_MODULE_ID_CNT)
-			return;
-		psc_regs = davinci_psc0_regs;
-		mdstat = &psc_regs->psc0.mdstat[id];
-		mdctl = &psc_regs->psc0.mdctl[id];
-	} else {
-		id -= DAVINCI_LPSC_PSC1_BASE;
-		if (id >= PSC_PSC1_MODULE_ID_CNT)
-			return;
-		psc_regs = davinci_psc1_regs;
-		mdstat = &psc_regs->psc1.mdstat[id];
-		mdctl = &psc_regs->psc1.mdctl[id];
-	}
-	ptstat = &psc_regs->ptstat;
-	ptcmd = &psc_regs->ptcmd;
-#endif
-
-	while (readl(ptstat) & 0x01)
-		continue;
-
-	if ((readl(mdstat) & 0x1f) == 0x03)
-		return; /* Already on and enabled */
-
-	writel(readl(mdctl) | 0x03, mdctl);
-
-	switch (id) {
-#ifdef CONFIG_SOC_DM644X
-	/* Special treatment for some modules as for sprue14 p.7.4.2 */
-	case DAVINCI_LPSC_VPSSSLV:
-	case DAVINCI_LPSC_EMAC:
-	case DAVINCI_LPSC_EMAC_WRAPPER:
-	case DAVINCI_LPSC_MDIO:
-	case DAVINCI_LPSC_USB:
-	case DAVINCI_LPSC_ATA:
-	case DAVINCI_LPSC_VLYNQ:
-	case DAVINCI_LPSC_UHPI:
-	case DAVINCI_LPSC_DDR_EMIF:
-	case DAVINCI_LPSC_AEMIF:
-	case DAVINCI_LPSC_MMC_SD:
-	case DAVINCI_LPSC_MEMSTICK:
-	case DAVINCI_LPSC_McBSP:
-	case DAVINCI_LPSC_GPIO:
-		writel(readl(mdctl) | 0x200, mdctl);
-		break;
-#endif
-	}
-
-	writel(0x01, ptcmd);
-
-	while (readl(ptstat) & 0x01)
-		continue;
-	while ((readl(mdstat) & 0x1f) != 0x03)
-		continue;
-}
-
-/* Not all DaVinci chips have a DSP power domain. */
-#ifdef CONFIG_SOC_DM644X
-
-/* If DSPLINK is used, we don't want U-Boot to power on the DSP. */
-#if !defined(CONFIG_SYS_USE_DSPLINK)
-void dsp_on(void)
-{
-	int i;
-
-	if (REG(PSC_PDSTAT1) & 0x1f)
-		return;			/* Already on */
-
-	REG(PSC_GBLCTL) |= 0x01;
-	REG(PSC_PDCTL1) |= 0x01;
-	REG(PSC_PDCTL1) &= ~0x100;
-	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03;
-	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff;
-	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03;
-	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff;
-	REG(PSC_PTCMD) = 0x02;
-
-	for (i = 0; i < 100; i++) {
-		if (REG(PSC_EPCPR) & 0x02)
-			break;
-	}
-
-	REG(PSC_CHP_SHRTSW) = 0x01;
-	REG(PSC_PDCTL1) |= 0x100;
-	REG(PSC_EPCCR) = 0x02;
-
-	for (i = 0; i < 100; i++) {
-		if (!(REG(PSC_PTSTAT) & 0x02))
-			break;
-	}
-
-	REG(PSC_GBLCTL) &= ~0x1f;
-}
-#endif /* CONFIG_SYS_USE_DSPLINK */
-
-#endif /* have a DSP */
diff --git a/cpu/arm926ejs/davinci/reset.S b/cpu/arm926ejs/davinci/reset.S
deleted file mode 100644
index ba0a7c3b4b..0000000000
--- a/cpu/arm926ejs/davinci/reset.S
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * Processor reset using WDT for TI TMS320DM644x SoC.
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * -----------------------------------------------------
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-.globl reset_cpu
-reset_cpu:
-	ldr	r0, WDT_TGCR
-	mov	r1, $0x08
-	str	r1, [r0]
-	ldr	r1, [r0]
-	orr	r1, r1, $0x03
-	str	r1, [r0]
-	mov	r1, $0
-	ldr	r0, WDT_TIM12
-	str	r1, [r0]
-	ldr	r0, WDT_TIM34
-	str	r1, [r0]
-	ldr	r0, WDT_PRD12
-	str	r1, [r0]
-	ldr	r0, WDT_PRD34
-	str	r1, [r0]
-	ldr	r0, WDT_TCR
-	ldr	r1, [r0]
-	orr	r1, r1, $0x40
-	str	r1, [r0]
-	ldr	r0, WDT_WDTCR
-	ldr	r1, [r0]
-	orr	r1, r1, $0x4000
-	str	r1, [r0]
-	ldr	r1, WDTCR_VAL1
-	str	r1, [r0]
-	ldr	r1, WDTCR_VAL2
-	str	r1, [r0]
-	/* Write an invalid value to the WDKEY field to trigger
-	 * an immediate watchdog reset */
-	mov     r1, $0x4000
-	str     r1, [r0]
-	nop
-	nop
-	nop
-	nop
-reset_cpu_loop:
-	b	reset_cpu_loop
-
-WDT_TGCR:
-	.word	0x01c21c24
-WDT_TIM12:
-	.word	0x01c21c10
-WDT_TIM34:
-	.word	0x01c21c14
-WDT_PRD12:
-	.word	0x01c21c18
-WDT_PRD34:
-	.word	0x01c21c1c
-WDT_TCR:
-	.word	0x01c21c20
-WDT_WDTCR:
-	.word	0x01c21c28
-WDTCR_VAL1:
-	.word	0xa5c64000
-WDTCR_VAL2:
-	.word	0xda7e4000
diff --git a/cpu/arm926ejs/davinci/timer.c b/cpu/arm926ejs/davinci/timer.c
deleted file mode 100644
index 9da7443f30..0000000000
--- a/cpu/arm926ejs/davinci/timer.c
+++ /dev/null
@@ -1,149 +0,0 @@
-/*
- * (C) Copyright 2003
- * Texas Instruments <www.ti.com>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002-2004
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * (C) Copyright 2004
- * Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-
-struct davinci_timer {
-	u_int32_t	pid12;
-	u_int32_t	emumgt;
-	u_int32_t	na1;
-	u_int32_t	na2;
-	u_int32_t	tim12;
-	u_int32_t	tim34;
-	u_int32_t	prd12;
-	u_int32_t	prd34;
-	u_int32_t	tcr;
-	u_int32_t	tgcr;
-	u_int32_t	wdtcr;
-};
-
-static struct davinci_timer * const timer =
-	(struct davinci_timer *)CONFIG_SYS_TIMERBASE;
-
-#define TIMER_LOAD_VAL	(CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)
-#define TIM_CLK_DIV	16
-
-static ulong timestamp;
-static ulong lastinc;
-
-int timer_init(void)
-{
-	/* We are using timer34 in unchained 32-bit mode, full speed */
-	writel(0x0, &timer->tcr);
-	writel(0x0, &timer->tgcr);
-	writel(0x06 | ((TIM_CLK_DIV - 1) << 8), &timer->tgcr);
-	writel(0x0, &timer->tim34);
-	writel(TIMER_LOAD_VAL, &timer->prd34);
-	lastinc = 0;
-	timestamp = 0;
-	writel(2 << 22, &timer->tcr);
-
-	return(0);
-}
-
-void reset_timer(void)
-{
-	writel(0x0, &timer->tcr);
-	writel(0x0, &timer->tim34);
-	lastinc = 0;
-	timestamp = 0;
-	writel(2 << 22, &timer->tcr);
-}
-
-static ulong get_timer_raw(void)
-{
-	ulong now = readl(&timer->tim34);
-
-	if (now >= lastinc) {
-		/* normal mode */
-		timestamp += now - lastinc;
-	} else {
-		/* overflow ... */
-		timestamp += now + TIMER_LOAD_VAL - lastinc;
-	}
-	lastinc = now;
-	return timestamp;
-}
-
-ulong get_timer(ulong base)
-{
-	return((get_timer_raw() / (TIMER_LOAD_VAL / TIM_CLK_DIV)) - base);
-}
-
-void set_timer(ulong t)
-{
-	timestamp = t;
-}
-
-void __udelay(unsigned long usec)
-{
-	ulong tmo;
-	ulong endtime;
-	signed long diff;
-
-	tmo = CONFIG_SYS_HZ_CLOCK / 1000;
-	tmo *= usec;
-	tmo /= (1000 * TIM_CLK_DIV);
-
-	endtime = get_timer_raw() + tmo;
-
-	do {
-		ulong now = get_timer_raw();
-		diff = endtime - now;
-	} while (diff >= 0);
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-	return(get_timer(0));
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
-	return CONFIG_SYS_HZ;
-}
diff --git a/cpu/arm926ejs/kirkwood/Makefile b/cpu/arm926ejs/kirkwood/Makefile
deleted file mode 100644
index fc2cc03001..0000000000
--- a/cpu/arm926ejs/kirkwood/Makefile
+++ /dev/null
@@ -1,49 +0,0 @@
-#
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
-# MA 02110-1301 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).a
-
-COBJS-y	= cpu.o
-COBJS-y	+= dram.o
-COBJS-y	+= mpp.o
-COBJS-y	+= timer.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS-y))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS)
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/cpu/arm926ejs/kirkwood/cpu.c b/cpu/arm926ejs/kirkwood/cpu.c
deleted file mode 100644
index 6fc3902580..0000000000
--- a/cpu/arm926ejs/kirkwood/cpu.c
+++ /dev/null
@@ -1,387 +0,0 @@
-/*
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/cache.h>
-#include <u-boot/md5.h>
-#include <asm/arch/kirkwood.h>
-#include <hush.h>
-
-#define BUFLEN	16
-
-void reset_cpu(unsigned long ignored)
-{
-	struct kwcpu_registers *cpureg =
-	    (struct kwcpu_registers *)KW_CPU_REG_BASE;
-
-	writel(readl(&cpureg->rstoutn_mask) | (1 << 2),
-		&cpureg->rstoutn_mask);
-	writel(readl(&cpureg->sys_soft_rst) | 1,
-		&cpureg->sys_soft_rst);
-	while (1) ;
-}
-
-/*
- * Generates Ramdom hex number reading some time varient system registers
- * and using md5 algorithm
- */
-unsigned char get_random_hex(void)
-{
-	int i;
-	u32 inbuf[BUFLEN];
-	u8 outbuf[BUFLEN];
-
-	/*
-	 * in case of 88F6281/88F6192 A0,
-	 * Bit7 need to reset to generate random values in KW_REG_UNDOC_0x1470
-	 * Soc reg offsets KW_REG_UNDOC_0x1470 and KW_REG_UNDOC_0x1478 are reserved regs and
-	 * Does not have names at this moment (no errata available)
-	 */
-	writel(readl(KW_REG_UNDOC_0x1478) & ~(1 << 7), KW_REG_UNDOC_0x1478);
-	for (i = 0; i < BUFLEN; i++) {
-		inbuf[i] = readl(KW_REG_UNDOC_0x1470);
-	}
-	md5((u8 *) inbuf, (BUFLEN * sizeof(u32)), outbuf);
-	return outbuf[outbuf[7] % 0x0f];
-}
-
-/*
- * Window Size
- * Used with the Base register to set the address window size and location.
- * Must be programmed from LSB to MSB as sequence of ones followed by
- * sequence of zeros. The number of ones specifies the size of the window in
- * 64 KByte granularity (e.g., a value of 0x00FF specifies 256 = 16 MByte).
- * NOTE: A value of 0x0 specifies 64-KByte size.
- */
-unsigned int kw_winctrl_calcsize(unsigned int sizeval)
-{
-	int i;
-	unsigned int j = 0;
-	u32 val = sizeval >> 1;
-
-	for (i = 0; val > 0x10000; i++) {
-		j |= (1 << i);
-		val = val >> 1;
-	}
-	return (0x0000ffff & j);
-}
-
-/*
- * kw_config_adr_windows - Configure address Windows
- *
- * There are 8 address windows supported by Kirkwood Soc to addess different
- * devices. Each window can be configured for size, BAR and remap addr
- * Below configuration is standard for most of the cases
- *
- * If remap function not used, remap_lo must be set as base
- *
- * Reference Documentation:
- * Mbus-L to Mbus Bridge Registers Configuration.
- * (Sec 25.1 and 25.3 of Datasheet)
- */
-int kw_config_adr_windows(void)
-{
-	struct kwwin_registers *winregs =
-		(struct kwwin_registers *)KW_CPU_WIN_BASE;
-
-	/* Window 0: PCIE MEM address space */
-	writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 256, KWCPU_TARGET_PCIE,
-		KWCPU_ATTR_PCIE_MEM, KWCPU_WIN_ENABLE), &winregs[0].ctrl);
-
-	writel(KW_DEFADR_PCI_MEM, &winregs[0].base);
-	writel(KW_DEFADR_PCI_MEM, &winregs[0].remap_lo);
-	writel(0x0, &winregs[0].remap_hi);
-
-	/* Window 1: PCIE IO address space */
-	writel(KWCPU_WIN_CTRL_DATA(1024 * 64, KWCPU_TARGET_PCIE,
-		KWCPU_ATTR_PCIE_IO, KWCPU_WIN_ENABLE), &winregs[1].ctrl);
-	writel(KW_DEFADR_PCI_IO, &winregs[1].base);
-	writel(KW_DEFADR_PCI_IO_REMAP, &winregs[1].remap_lo);
-	writel(0x0, &winregs[1].remap_hi);
-
-	/* Window 2: NAND Flash address space */
-	writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
-		KWCPU_ATTR_NANDFLASH, KWCPU_WIN_ENABLE), &winregs[2].ctrl);
-	writel(KW_DEFADR_NANDF, &winregs[2].base);
-	writel(KW_DEFADR_NANDF, &winregs[2].remap_lo);
-	writel(0x0, &winregs[2].remap_hi);
-
-	/* Window 3: SPI Flash address space */
-	writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
-		KWCPU_ATTR_SPIFLASH, KWCPU_WIN_ENABLE), &winregs[3].ctrl);
-	writel(KW_DEFADR_SPIF, &winregs[3].base);
-	writel(KW_DEFADR_SPIF, &winregs[3].remap_lo);
-	writel(0x0, &winregs[3].remap_hi);
-
-	/* Window 4: BOOT Memory address space */
-	writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
-		KWCPU_ATTR_BOOTROM, KWCPU_WIN_ENABLE), &winregs[4].ctrl);
-	writel(KW_DEFADR_BOOTROM, &winregs[4].base);
-
-	/* Window 5: Security SRAM address space */
-	writel(KWCPU_WIN_CTRL_DATA(1024 * 64, KWCPU_TARGET_SASRAM,
-		KWCPU_ATTR_SASRAM, KWCPU_WIN_ENABLE), &winregs[5].ctrl);
-	writel(KW_DEFADR_SASRAM, &winregs[5].base);
-
-	/* Window 6-7: Disabled */
-	writel(KWCPU_WIN_DISABLE, &winregs[6].ctrl);
-	writel(KWCPU_WIN_DISABLE, &winregs[7].ctrl);
-
-	return 0;
-}
-
-/*
- * kw_config_gpio - GPIO configuration
- */
-void kw_config_gpio(u32 gpp0_oe_val, u32 gpp1_oe_val, u32 gpp0_oe, u32 gpp1_oe)
-{
-	struct kwgpio_registers *gpio0reg =
-		(struct kwgpio_registers *)KW_GPIO0_BASE;
-	struct kwgpio_registers *gpio1reg =
-		(struct kwgpio_registers *)KW_GPIO1_BASE;
-
-	/* Init GPIOS to default values as per board requirement */
-	writel(gpp0_oe_val, &gpio0reg->dout);
-	writel(gpp1_oe_val, &gpio1reg->dout);
-	writel(gpp0_oe, &gpio0reg->oe);
-	writel(gpp1_oe, &gpio1reg->oe);
-}
-
-/*
- * kw_config_mpp - Multi-Purpose Pins Functionality configuration
- *
- * Each MPP can be configured to different functionality through
- * MPP control register, ref (sec 6.1 of kirkwood h/w specification)
- *
- * There are maximum 64 Multi-Pourpose Pins on Kirkwood
- * Each MPP functionality can be configuration by a 4bit value
- * of MPP control reg, the value and associated functionality depends
- * upon used SoC varient
- */
-int kw_config_mpp(u32 mpp0_7, u32 mpp8_15, u32 mpp16_23, u32 mpp24_31,
-		u32 mpp32_39, u32 mpp40_47, u32 mpp48_55)
-{
-	u32 *mppreg = (u32 *) KW_MPP_BASE;
-
-	/* program mpp registers */
-	writel(mpp0_7, &mppreg[0]);
-	writel(mpp8_15, &mppreg[1]);
-	writel(mpp16_23, &mppreg[2]);
-	writel(mpp24_31, &mppreg[3]);
-	writel(mpp32_39, &mppreg[4]);
-	writel(mpp40_47, &mppreg[5]);
-	writel(mpp48_55, &mppreg[6]);
-	return 0;
-}
-
-/*
- * SYSRSTn Duration Counter Support
- *
- * Kirkwood SoC implements a hardware-based SYSRSTn duration counter.
- * When SYSRSTn is asserted low, a SYSRSTn duration counter is running.
- * The SYSRSTn duration counter is useful for implementing a manufacturer
- * or factory reset. Upon a long reset assertion that is greater than a
- * pre-configured environment variable value for sysrstdelay,
- * The counter value is stored in the SYSRSTn Length Counter Register
- * The counter is based on the 25-MHz reference clock (40ns)
- * It is a 29-bit counter, yielding a maximum counting duration of
- * 2^29/25 MHz (21.4 seconds). When the counter reach its maximum value,
- * it remains at this value until counter reset is triggered by setting
- * bit 31 of KW_REG_SYSRST_CNT
- */
-static void kw_sysrst_action(void)
-{
-	int ret;
-	char *s = getenv("sysrstcmd");
-
-	if (!s) {
-		debug("Error.. %s failed, check sysrstcmd\n",
-			__FUNCTION__);
-		return;
-	}
-
-	debug("Starting %s process...\n", __FUNCTION__);
-#if !defined(CONFIG_SYS_HUSH_PARSER)
-	ret = run_command (s, 0);
-#else
-	ret = parse_string_outer(s, FLAG_PARSE_SEMICOLON
-				  | FLAG_EXIT_FROM_LOOP);
-#endif
-	if (ret < 0)
-		debug("Error.. %s failed\n", __FUNCTION__);
-	else
-		debug("%s process finished\n", __FUNCTION__);
-}
-
-static void kw_sysrst_check(void)
-{
-	u32 sysrst_cnt, sysrst_dly;
-	char *s;
-
-	/*
-	 * no action if sysrstdelay environment variable is not defined
-	 */
-	s = getenv("sysrstdelay");
-	if (s == NULL)
-		return;
-
-	/* read sysrstdelay value */
-	sysrst_dly = (u32) simple_strtoul(s, NULL, 10);
-
-	/* read SysRst Length counter register (bits 28:0) */
-	sysrst_cnt = (0x1fffffff & readl(KW_REG_SYSRST_CNT));
-	debug("H/w Rst hold time: %d.%d secs\n",
-		sysrst_cnt / SYSRST_CNT_1SEC_VAL,
-		sysrst_cnt % SYSRST_CNT_1SEC_VAL);
-
-	/* clear the counter for next valid read*/
-	writel(1 << 31, KW_REG_SYSRST_CNT);
-
-	/*
-	 * sysrst_action:
-	 * if H/w Reset key is pressed and hold for time
-	 * more than sysrst_dly in seconds
-	 */
-	if (sysrst_cnt >= SYSRST_CNT_1SEC_VAL * sysrst_dly)
-		kw_sysrst_action();
-}
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo(void)
-{
-	char *name = "Unknown";
-
-	switch (readl(KW_REG_DEVICE_ID) & 0x03) {
-	case 1:
-		name = "88F6192_A0";
-		break;
-	case 2:
-		name = "88F6281_A0";
-		break;
-	default:
-		printf("SoC:   Unsupported Kirkwood\n");
-		return -1;
-	}
-	printf("SoC:   Kirkwood %s\n", name);
-	return 0;
-}
-#endif /* CONFIG_DISPLAY_CPUINFO */
-
-#ifdef CONFIG_ARCH_CPU_INIT
-int arch_cpu_init(void)
-{
-	u32 reg;
-	struct kwcpu_registers *cpureg =
-		(struct kwcpu_registers *)KW_CPU_REG_BASE;
-
-	/* Linux expects` the internal registers to be at 0xf1000000 */
-	writel(KW_REGS_PHY_BASE, KW_OFFSET_REG);
-
-	/* Enable and invalidate L2 cache in write through mode */
-	writel(readl(&cpureg->l2_cfg) | 0x18, &cpureg->l2_cfg);
-	invalidate_l2_cache();
-
-	kw_config_adr_windows();
-
-#ifdef CONFIG_KIRKWOOD_RGMII_PAD_1V8
-	/*
-	 * Configures the I/O voltage of the pads connected to Egigabit
-	 * Ethernet interface to 1.8V
-	 * By defult it is set to 3.3V
-	 */
-	reg = readl(KW_REG_MPP_OUT_DRV_REG);
-	reg |= (1 << 7);
-	writel(reg, KW_REG_MPP_OUT_DRV_REG);
-#endif
-#ifdef CONFIG_KIRKWOOD_EGIGA_INIT
-	/*
-	 * Set egiga port0/1 in normal functional mode
-	 * This is required becasue on kirkwood by default ports are in reset mode
-	 * OS egiga driver may not have provision to set them in normal mode
-	 * and if u-boot is build without network support, network may fail at OS level
-	 */
-	reg = readl(KWGBE_PORT_SERIAL_CONTROL1_REG(0));
-	reg &= ~(1 << 4);	/* Clear PortReset Bit */
-	writel(reg, (KWGBE_PORT_SERIAL_CONTROL1_REG(0)));
-	reg = readl(KWGBE_PORT_SERIAL_CONTROL1_REG(1));
-	reg &= ~(1 << 4);	/* Clear PortReset Bit */
-	writel(reg, (KWGBE_PORT_SERIAL_CONTROL1_REG(1)));
-#endif
-#ifdef CONFIG_KIRKWOOD_PCIE_INIT
-	/*
-	 * Enable PCI Express Port0
-	 */
-	reg = readl(&cpureg->ctrl_stat);
-	reg |= (1 << 0);	/* Set PEX0En Bit */
-	writel(reg, &cpureg->ctrl_stat);
-#endif
-	return 0;
-}
-#endif /* CONFIG_ARCH_CPU_INIT */
-
-/*
- * SOC specific misc init
- */
-#if defined(CONFIG_ARCH_MISC_INIT)
-int arch_misc_init(void)
-{
-	volatile u32 temp;
-
-	/*CPU streaming & write allocate */
-	temp = readfr_extra_feature_reg();
-	temp &= ~(1 << 28);	/* disable wr alloc */
-	writefr_extra_feature_reg(temp);
-
-	temp = readfr_extra_feature_reg();
-	temp &= ~(1 << 29);	/* streaming disabled */
-	writefr_extra_feature_reg(temp);
-
-	/* L2Cache settings */
-	temp = readfr_extra_feature_reg();
-	/* Disable L2C pre fetch - Set bit 24 */
-	temp |= (1 << 24);
-	/* enable L2C - Set bit 22 */
-	temp |= (1 << 22);
-	writefr_extra_feature_reg(temp);
-
-	icache_enable();
-	/* Change reset vector to address 0x0 */
-	temp = get_cr();
-	set_cr(temp & ~CR_V);
-
-	/* checks and execute resset to factory event */
-	kw_sysrst_check();
-
-	return 0;
-}
-#endif /* CONFIG_ARCH_MISC_INIT */
-
-#ifdef CONFIG_KIRKWOOD_EGIGA
-int cpu_eth_init(bd_t *bis)
-{
-	kirkwood_egiga_initialize(bis);
-	return 0;
-}
-#endif
diff --git a/cpu/arm926ejs/kirkwood/dram.c b/cpu/arm926ejs/kirkwood/dram.c
deleted file mode 100644
index 8f2a18af6b..0000000000
--- a/cpu/arm926ejs/kirkwood/dram.c
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <config.h>
-#include <asm/arch/kirkwood.h>
-
-#define KW_REG_CPUCS_WIN_BAR(x)		(KW_REGISTER(0x1500) + (x * 0x08))
-#define KW_REG_CPUCS_WIN_SZ(x)		(KW_REGISTER(0x1504) + (x * 0x08))
-/*
- * kw_sdram_bar - reads SDRAM Base Address Register
- */
-u32 kw_sdram_bar(enum memory_bank bank)
-{
-	u32 result = 0;
-	u32 enable = 0x01 & readl(KW_REG_CPUCS_WIN_SZ(bank));
-
-	if ((!enable) || (bank > BANK3))
-		return 0;
-
-	result = readl(KW_REG_CPUCS_WIN_BAR(bank));
-	return result;
-}
-
-/*
- * kw_sdram_bs - reads SDRAM Bank size
- */
-u32 kw_sdram_bs(enum memory_bank bank)
-{
-	u32 result = 0;
-	u32 enable = 0x01 & readl(KW_REG_CPUCS_WIN_SZ(bank));
-
-	if ((!enable) || (bank > BANK3))
-		return 0;
-	result = 0xff000000 & readl(KW_REG_CPUCS_WIN_SZ(bank));
-	result += 0x01000000;
-	return result;
-}
diff --git a/cpu/arm926ejs/kirkwood/mpp.c b/cpu/arm926ejs/kirkwood/mpp.c
deleted file mode 100644
index b2f0ad55e3..0000000000
--- a/cpu/arm926ejs/kirkwood/mpp.c
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * arch/arm/mach-kirkwood/mpp.c
- *
- * MPP functions for Marvell Kirkwood SoCs
- * Referenced from Linux kernel source
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <common.h>
-#include <asm/arch/kirkwood.h>
-#include <asm/arch/mpp.h>
-
-static u32 kirkwood_variant(void)
-{
-	switch (readl(KW_REG_DEVICE_ID) & 0x03) {
-	case 1:
-		return MPP_F6192_MASK;
-	case 2:
-		return MPP_F6281_MASK;
-	default:
-		debug("MPP setup: unknown kirkwood variant\n");
-		return 0;
-	}
-}
-
-#define MPP_CTRL(i)	(KW_MPP_BASE + (i* 4))
-#define MPP_NR_REGS	(1 + MPP_MAX/8)
-
-void kirkwood_mpp_conf(u32 *mpp_list)
-{
-	u32 mpp_ctrl[MPP_NR_REGS];
-	unsigned int variant_mask;
-	int i;
-
-	variant_mask = kirkwood_variant();
-	if (!variant_mask)
-		return;
-
-	debug( "initial MPP regs:");
-	for (i = 0; i < MPP_NR_REGS; i++) {
-		mpp_ctrl[i] = readl(MPP_CTRL(i));
-		debug(" %08x", mpp_ctrl[i]);
-	}
-	debug("\n");
-
-
-	while (*mpp_list) {
-		unsigned int num = MPP_NUM(*mpp_list);
-		unsigned int sel = MPP_SEL(*mpp_list);
-		int shift;
-
-		if (num > MPP_MAX) {
-			debug("kirkwood_mpp_conf: invalid MPP "
-					"number (%u)\n", num);
-			continue;
-		}
-		if (!(*mpp_list & variant_mask)) {
-			debug("kirkwood_mpp_conf: requested MPP%u config "
-				"unavailable on this hardware\n", num);
-			continue;
-		}
-
-		shift = (num & 7) << 2;
-		mpp_ctrl[num / 8] &= ~(0xf << shift);
-		mpp_ctrl[num / 8] |= sel << shift;
-
-		mpp_list++;
-	}
-
-	debug("  final MPP regs:");
-	for (i = 0; i < MPP_NR_REGS; i++) {
-		writel(mpp_ctrl[i], MPP_CTRL(i));
-		debug(" %08x", mpp_ctrl[i]);
-	}
-	debug("\n");
-
-}
diff --git a/cpu/arm926ejs/kirkwood/timer.c b/cpu/arm926ejs/kirkwood/timer.c
deleted file mode 100644
index 2ec6a93807..0000000000
--- a/cpu/arm926ejs/kirkwood/timer.c
+++ /dev/null
@@ -1,168 +0,0 @@
-/*
- * Copyright (C) Marvell International Ltd. and its affiliates
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <common.h>
-#include <asm/arch/kirkwood.h>
-
-#define UBOOT_CNTR	0	/* counter to use for uboot timer */
-
-/* Timer reload and current value registers */
-struct kwtmr_val {
-	u32 reload;	/* Timer reload reg */
-	u32 val;	/* Timer value reg */
-};
-
-/* Timer registers */
-struct kwtmr_registers {
-	u32 ctrl;	/* Timer control reg */
-	u32 pad[3];
-	struct kwtmr_val tmr[2];
-	u32 wdt_reload;
-	u32 wdt_val;
-};
-
-struct kwtmr_registers *kwtmr_regs = (struct kwtmr_registers *)KW_TIMER_BASE;
-
-/*
- * ARM Timers Registers Map
- */
-#define CNTMR_CTRL_REG			&kwtmr_regs->ctrl
-#define CNTMR_RELOAD_REG(tmrnum)	&kwtmr_regs->tmr[tmrnum].reload
-#define CNTMR_VAL_REG(tmrnum)		&kwtmr_regs->tmr[tmrnum].val
-
-/*
- * ARM Timers Control Register
- * CPU_TIMERS_CTRL_REG (CTCR)
- */
-#define CTCR_ARM_TIMER_EN_OFFS(cntr)	(cntr * 2)
-#define CTCR_ARM_TIMER_EN_MASK(cntr)	(1 << CTCR_ARM_TIMER_EN_OFFS)
-#define CTCR_ARM_TIMER_EN(cntr)		(1 << CTCR_ARM_TIMER_EN_OFFS(cntr))
-#define CTCR_ARM_TIMER_DIS(cntr)	(0 << CTCR_ARM_TIMER_EN_OFFS(cntr))
-
-#define CTCR_ARM_TIMER_AUTO_OFFS(cntr)	((cntr * 2) + 1)
-#define CTCR_ARM_TIMER_AUTO_MASK(cntr)	(1 << 1)
-#define CTCR_ARM_TIMER_AUTO_EN(cntr)	(1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
-#define CTCR_ARM_TIMER_AUTO_DIS(cntr)	(0 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
-
-/*
- * ARM Timer\Watchdog Reload Register
- * CNTMR_RELOAD_REG (TRR)
- */
-#define TRG_ARM_TIMER_REL_OFFS		0
-#define TRG_ARM_TIMER_REL_MASK		0xffffffff
-
-/*
- * ARM Timer\Watchdog Register
- * CNTMR_VAL_REG (TVRG)
- */
-#define TVR_ARM_TIMER_OFFS		0
-#define TVR_ARM_TIMER_MASK		0xffffffff
-#define TVR_ARM_TIMER_MAX		0xffffffff
-#define TIMER_LOAD_VAL 			0xffffffff
-
-#define READ_TIMER			(readl(CNTMR_VAL_REG(UBOOT_CNTR)) /	\
-					 (CONFIG_SYS_TCLK / 1000))
-
-static ulong timestamp;
-static ulong lastdec;
-
-void reset_timer_masked(void)
-{
-	/* reset time */
-	lastdec = READ_TIMER;
-	timestamp = 0;
-}
-
-ulong get_timer_masked(void)
-{
-	ulong now = READ_TIMER;
-
-	if (lastdec >= now) {
-		/* normal mode */
-		timestamp += lastdec - now;
-	} else {
-		/* we have an overflow ... */
-		timestamp += lastdec +
-			(TIMER_LOAD_VAL / (CONFIG_SYS_TCLK / 1000)) - now;
-	}
-	lastdec = now;
-
-	return timestamp;
-}
-
-void reset_timer(void)
-{
-	reset_timer_masked();
-}
-
-ulong get_timer(ulong base)
-{
-	return get_timer_masked() - base;
-}
-
-void set_timer(ulong t)
-{
-	timestamp = t;
-}
-
-void __udelay(unsigned long usec)
-{
-	uint current;
-	ulong delayticks;
-
-	current = readl(CNTMR_VAL_REG(UBOOT_CNTR));
-	delayticks = (usec * (CONFIG_SYS_TCLK / 1000000));
-
-	if (current < delayticks) {
-		delayticks -= current;
-		while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) < current) ;
-		while ((TIMER_LOAD_VAL - delayticks) <
-			readl(CNTMR_VAL_REG(UBOOT_CNTR))) ;
-	} else {
-		while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) >
-			(current - delayticks)) ;
-	}
-}
-
-/*
- * init the counter
- */
-int timer_init(void)
-{
-	unsigned int cntmrctrl;
-
-	/* load value into timer */
-	writel(TIMER_LOAD_VAL, CNTMR_RELOAD_REG(UBOOT_CNTR));
-	writel(TIMER_LOAD_VAL, CNTMR_VAL_REG(UBOOT_CNTR));
-
-	/* enable timer in auto reload mode */
-	cntmrctrl = readl(CNTMR_CTRL_REG);
-	cntmrctrl |= CTCR_ARM_TIMER_EN(UBOOT_CNTR);
-	cntmrctrl |= CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR);
-	writel(cntmrctrl, CNTMR_CTRL_REG);
-
-	/* init the timestamp and lastdec value */
-	reset_timer_masked();
-
-	return 0;
-}
diff --git a/cpu/arm926ejs/mx25/Makefile b/cpu/arm926ejs/mx25/Makefile
deleted file mode 100644
index 55c1e899be..0000000000
--- a/cpu/arm926ejs/mx25/Makefile
+++ /dev/null
@@ -1,46 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).a
-
-COBJS	= generic.o timer.o
-MX27OBJS = reset.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-SRCS	+= $(addprefix $(SRCTREE)/cpu/arm926ejs/mx27/,$(MX27OBJS:.o=.c))
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS) $(MX27OBJS))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS)
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/cpu/arm926ejs/mx25/generic.c b/cpu/arm926ejs/mx25/generic.c
deleted file mode 100644
index 694841dd10..0000000000
--- a/cpu/arm926ejs/mx25/generic.c
+++ /dev/null
@@ -1,263 +0,0 @@
-/*
- * (C) Copyright 2009 DENX Software Engineering
- * Author: John Rigby <jrigby@gmail.com>
- *
- * Based on mx27/generic.c:
- *  Copyright (c) 2008 Eric Jarrige <eric.jarrige@armadeus.org>
- *  Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <div64.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/imx25-pinmux.h>
-#ifdef CONFIG_MXC_MMC
-#include <asm/arch/mxcmmc.h>
-#endif
-
-/*
- *  get the system pll clock in Hz
- *
- *                  mfi + mfn / (mfd +1)
- *  f = 2 * f_ref * --------------------
- *                        pd + 1
- */
-static unsigned int imx_decode_pll (unsigned int pll, unsigned int f_ref)
-{
-	unsigned int mfi = (pll >> CCM_PLL_MFI_SHIFT)
-	    & CCM_PLL_MFI_MASK;
-	unsigned int mfn = (pll >> CCM_PLL_MFN_SHIFT)
-	    & CCM_PLL_MFN_MASK;
-	unsigned int mfd = (pll >> CCM_PLL_MFD_SHIFT)
-	    & CCM_PLL_MFD_MASK;
-	unsigned int pd = (pll >> CCM_PLL_PD_SHIFT)
-	    & CCM_PLL_PD_MASK;
-
-	mfi = mfi <= 5 ? 5 : mfi;
-
-	return lldiv (2 * (u64) f_ref * (mfi * (mfd + 1) + mfn),
-		      (mfd + 1) * (pd + 1));
-}
-
-static ulong imx_get_mpllclk (void)
-{
-	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
-	ulong fref = 24000000;
-
-	return imx_decode_pll (readl (&ccm->mpctl), fref);
-}
-
-ulong imx_get_armclk (void)
-{
-	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
-	ulong cctl = readl (&ccm->cctl);
-	ulong fref = imx_get_mpllclk ();
-	ulong div;
-
-	if (cctl & CCM_CCTL_ARM_SRC)
-		fref = lldiv ((fref * 3), 4);
-
-	div = ((cctl >> CCM_CCTL_ARM_DIV_SHIFT)
-	       & CCM_CCTL_ARM_DIV_MASK) + 1;
-
-	return lldiv (fref, div);
-}
-
-ulong imx_get_ahbclk (void)
-{
-	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
-	ulong cctl = readl (&ccm->cctl);
-	ulong fref = imx_get_armclk ();
-	ulong div;
-
-	div = ((cctl >> CCM_CCTL_AHB_DIV_SHIFT)
-	       & CCM_CCTL_AHB_DIV_MASK) + 1;
-
-	return lldiv (fref, div);
-}
-
-ulong imx_get_perclk (int clk)
-{
-	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
-	ulong fref = imx_get_ahbclk ();
-	ulong div;
-
-	div = readl (&ccm->pcdr[CCM_PERCLK_REG (clk)]);
-	div = ((div >> CCM_PERCLK_SHIFT (clk)) & CCM_PERCLK_MASK) + 1;
-
-	return lldiv (fref, div);
-}
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo (void)
-{
-	char buf[32];
-
-	printf ("CPU:   Freescale i.MX25 at %s MHz\n\n",
-		strmhz (buf, imx_get_mpllclk ()));
-	return 0;
-}
-#endif
-
-int cpu_eth_init (bd_t * bis)
-{
-#if defined(CONFIG_FEC_MXC)
-	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
-	ulong val;
-
-	val = readl (&ccm->cgr0);
-	val |= (1 << 23);
-	writel (val, &ccm->cgr0);
-	return fecmxc_initialize (bis);
-#else
-	return 0;
-#endif
-}
-
-/*
- * Initializes on-chip MMC controllers.
- * to override, implement board_mmc_init()
- */
-int cpu_mmc_init (bd_t * bis)
-{
-#ifdef CONFIG_MXC_MMC
-	return mxc_mmc_init (bis);
-#else
-	return 0;
-#endif
-}
-
-#ifdef CONFIG_MXC_UART
-void mx25_uart_init_pins (void)
-{
-	struct iomuxc_mux_ctl *muxctl;
-	struct iomuxc_pad_ctl *padctl;
-	u32 inpadctl;
-	u32 outpadctl;
-	u32 muxmode0;
-
-	muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
-	padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
-	muxmode0 = MX25_PIN_MUX_MODE (0);
-	/*
-	 * set up input pins with hysteresis and 100K pull-ups
-	 */
-	inpadctl = MX25_PIN_PAD_CTL_HYS
-	    | MX25_PIN_PAD_CTL_PKE
-	    | MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PU;
-
-	/*
-	 * set up output pins with 100K pull-downs
-	 * FIXME: need to revisit this
-	 *      PUE is ignored if PKE is not set
-	 *      so the right value here is likely
-	 *        0x0 for no pull up/down
-	 *      or
-	 *        0xc0 for 100k pull down
-	 */
-	outpadctl = MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD;
-
-	/* UART1 */
-	/* rxd */
-	writel (muxmode0, &muxctl->pad_uart1_rxd);
-	writel (inpadctl, &padctl->pad_uart1_rxd);
-
-	/* txd */
-	writel (muxmode0, &muxctl->pad_uart1_txd);
-	writel (outpadctl, &padctl->pad_uart1_txd);
-
-	/* rts */
-	writel (muxmode0, &muxctl->pad_uart1_rts);
-	writel (outpadctl, &padctl->pad_uart1_rts);
-
-	/* cts */
-	writel (muxmode0, &muxctl->pad_uart1_cts);
-	writel (inpadctl, &padctl->pad_uart1_cts);
-}
-#endif /* CONFIG_MXC_UART */
-
-#ifdef CONFIG_FEC_MXC
-void mx25_fec_init_pins (void)
-{
-	struct iomuxc_mux_ctl *muxctl;
-	struct iomuxc_pad_ctl *padctl;
-	u32 inpadctl_100kpd;
-	u32 inpadctl_22kpu;
-	u32 outpadctl;
-	u32 muxmode0;
-
-	muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
-	padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
-	muxmode0 = MX25_PIN_MUX_MODE (0);
-	inpadctl_100kpd = MX25_PIN_PAD_CTL_HYS
-	    | MX25_PIN_PAD_CTL_PKE
-	    | MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD;
-	inpadctl_22kpu = MX25_PIN_PAD_CTL_HYS
-	    | MX25_PIN_PAD_CTL_PKE
-	    | MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_22K_PU;
-	/*
-	 * set up output pins with 100K pull-downs
-	 * FIXME: need to revisit this
-	 *      PUE is ignored if PKE is not set
-	 *      so the right value here is likely
-	 *        0x0 for no pull
-	 *      or
-	 *        0xc0 for 100k pull down
-	 */
-	outpadctl = MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD;
-
-	/* FEC_TX_CLK */
-	writel (muxmode0, &muxctl->pad_fec_tx_clk);
-	writel (inpadctl_100kpd, &padctl->pad_fec_tx_clk);
-
-	/* FEC_RX_DV */
-	writel (muxmode0, &muxctl->pad_fec_rx_dv);
-	writel (inpadctl_100kpd, &padctl->pad_fec_rx_dv);
-
-	/* FEC_RDATA0 */
-	writel (muxmode0, &muxctl->pad_fec_rdata0);
-	writel (inpadctl_100kpd, &padctl->pad_fec_rdata0);
-
-	/* FEC_TDATA0 */
-	writel (muxmode0, &muxctl->pad_fec_tdata0);
-	writel (outpadctl, &padctl->pad_fec_tdata0);
-
-	/* FEC_TX_EN */
-	writel (muxmode0, &muxctl->pad_fec_tx_en);
-	writel (outpadctl, &padctl->pad_fec_tx_en);
-
-	/* FEC_MDC */
-	writel (muxmode0, &muxctl->pad_fec_mdc);
-	writel (outpadctl, &padctl->pad_fec_mdc);
-
-	/* FEC_MDIO */
-	writel (muxmode0, &muxctl->pad_fec_mdio);
-	writel (inpadctl_22kpu, &padctl->pad_fec_mdio);
-
-	/* FEC_RDATA1 */
-	writel (muxmode0, &muxctl->pad_fec_rdata1);
-	writel (inpadctl_100kpd, &padctl->pad_fec_rdata1);
-
-	/* FEC_TDATA1 */
-	writel (muxmode0, &muxctl->pad_fec_tdata1);
-	writel (outpadctl, &padctl->pad_fec_tdata1);
-
-}
-#endif /* CONFIG_FEC_MXC */
diff --git a/cpu/arm926ejs/mx25/reset.c b/cpu/arm926ejs/mx25/reset.c
deleted file mode 100644
index 1e33150eb9..0000000000
--- a/cpu/arm926ejs/mx25/reset.c
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * (C) Copyright 2009
- * Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-
-/*
- * Reset the cpu by setting up the watchdog timer and let it time out
- */
-void reset_cpu (ulong ignored)
-{
-	struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE;
-	/* Disable watchdog and set Time-Out field to 0 */
-	writel (0x00000000, &regs->wcr);
-
-	/* Write Service Sequence */
-	writel (0x00005555, &regs->wsr);
-	writel (0x0000AAAA, &regs->wsr);
-
-	/* Enable watchdog */
-	writel (WCR_WDE, &regs->wcr);
-
-	while (1) ;
-}
diff --git a/cpu/arm926ejs/mx25/timer.c b/cpu/arm926ejs/mx25/timer.c
deleted file mode 100644
index 11d41a8bf9..0000000000
--- a/cpu/arm926ejs/mx25/timer.c
+++ /dev/null
@@ -1,187 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * (C) Copyright 2009
- * Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
- *
- * (C) Copyright 2009 DENX Software Engineering
- * Author: John Rigby <jrigby@gmail.com>
- * 	Add support for MX25
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <div64.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-
-static ulong timestamp;
-static ulong lastinc;
-
-/*
- * "time" is measured in 1 / CONFIG_SYS_HZ seconds,
- * "tick" is internal timer period
- */
-#ifdef CONFIG_MX25_TIMER_HIGH_PRECISION
-/* ~0.4% error - measured with stop-watch on 100s boot-delay */
-static inline unsigned long long tick_to_time(unsigned long long tick)
-{
-	tick *= CONFIG_SYS_HZ;
-	do_div(tick, CONFIG_MX25_CLK32);
-	return tick;
-}
-
-static inline unsigned long long time_to_tick(unsigned long long time)
-{
-	time *= CONFIG_MX25_CLK32;
-	do_div(time, CONFIG_SYS_HZ);
-	return time;
-}
-
-static inline unsigned long long us_to_tick(unsigned long long us)
-{
-	us = us * CONFIG_MX25_CLK32 + 999999;
-	do_div(us, 1000000);
-	return us;
-}
-#else
-/* ~2% error */
-#define TICK_PER_TIME	((CONFIG_MX25_CLK32 + CONFIG_SYS_HZ / 2) / \
-		CONFIG_SYS_HZ)
-#define US_PER_TICK	(1000000 / CONFIG_MX25_CLK32)
-
-static inline unsigned long long tick_to_time(unsigned long long tick)
-{
-	do_div(tick, TICK_PER_TIME);
-	return tick;
-}
-
-static inline unsigned long long time_to_tick(unsigned long long time)
-{
-	return time * TICK_PER_TIME;
-}
-
-static inline unsigned long long us_to_tick(unsigned long long us)
-{
-	us += US_PER_TICK - 1;
-	do_div(us, US_PER_TICK);
-	return us;
-}
-#endif
-
-/* nothing really to do with interrupts, just starts up a counter. */
-/* The 32KHz 32-bit timer overruns in 134217 seconds */
-int timer_init(void)
-{
-	int i;
-	struct gpt_regs *gpt = (struct gpt_regs *)IMX_GPT1_BASE;
-	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
-
-	/* setup GP Timer 1 */
-	writel(GPT_CTRL_SWR, &gpt->ctrl);
-
-	writel(readl(&ccm->cgr1) | CCM_CGR1_GPT1, &ccm->cgr1);
-
-	for (i = 0; i < 100; i++)
-		writel(0, &gpt->ctrl); /* We have no udelay by now */
-	writel(0, &gpt->pre); /* prescaler = 1 */
-	/* Freerun Mode, 32KHz input */
-	writel(readl(&gpt->ctrl) | GPT_CTRL_CLKSOURCE_32 | GPT_CTRL_FRR,
-			&gpt->ctrl);
-	writel(readl(&gpt->ctrl) | GPT_CTRL_TEN, &gpt->ctrl);
-
-	return 0;
-}
-
-void reset_timer_masked(void)
-{
-	struct gpt_regs *gpt = (struct gpt_regs *)IMX_GPT1_BASE;
-	/* reset time */
-	/* capture current incrementer value time */
-	lastinc = readl(&gpt->counter);
-	timestamp = 0; /* start "advancing" time stamp from 0 */
-}
-
-void reset_timer(void)
-{
-	reset_timer_masked();
-}
-
-unsigned long long get_ticks (void)
-{
-	struct gpt_regs *gpt = (struct gpt_regs *)IMX_GPT1_BASE;
-	ulong now = readl(&gpt->counter); /* current tick value */
-
-	if (now >= lastinc) {
-		/*
-		 * normal mode (non roll)
-		 * move stamp forward with absolut diff ticks
-		 */
-		timestamp += (now - lastinc);
-	} else {
-		/* we have rollover of incrementer */
-		timestamp += (0xFFFFFFFF - lastinc) + now;
-	}
-	lastinc = now;
-	return timestamp;
-}
-
-ulong get_timer_masked (void)
-{
-	/*
-	 * get_ticks() returns a long long (64 bit), it wraps in
-	 * 2^64 / CONFIG_MX25_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
-	 * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
-	 * 5 * 10^6 days - long enough.
-	 */
-	return tick_to_time(get_ticks());
-}
-
-ulong get_timer (ulong base)
-{
-	return get_timer_masked () - base;
-}
-
-void set_timer (ulong t)
-{
-	timestamp = time_to_tick(t);
-}
-
-/* delay x useconds AND preserve advance timstamp value */
-void __udelay (unsigned long usec)
-{
-	unsigned long long tmp;
-	ulong tmo;
-
-	tmo = us_to_tick(usec);
-	tmp = get_ticks() + tmo;	/* get current timestamp */
-
-	while (get_ticks() < tmp)	/* loop till event */
-		 /*NOP*/;
-}
diff --git a/cpu/arm926ejs/mx27/Makefile b/cpu/arm926ejs/mx27/Makefile
deleted file mode 100644
index 67d1b0e303..0000000000
--- a/cpu/arm926ejs/mx27/Makefile
+++ /dev/null
@@ -1,44 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).a
-
-COBJS	= generic.o reset.o timer.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS)
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/cpu/arm926ejs/mx27/generic.c b/cpu/arm926ejs/mx27/generic.c
deleted file mode 100644
index 30cf544712..0000000000
--- a/cpu/arm926ejs/mx27/generic.c
+++ /dev/null
@@ -1,335 +0,0 @@
-/*
- *  Copyright (c) 2008 Eric Jarrige <eric.jarrige@armadeus.org>
- *  Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <div64.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#ifdef CONFIG_MXC_MMC
-#include <asm/arch/mxcmmc.h>
-#endif
-
-/*
- *  get the system pll clock in Hz
- *
- *                  mfi + mfn / (mfd +1)
- *  f = 2 * f_ref * --------------------
- *                        pd + 1
- */
-unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref)
-{
-	unsigned int mfi = (pll >> 10) & 0xf;
-	unsigned int mfn = pll & 0x3ff;
-	unsigned int mfd = (pll >> 16) & 0x3ff;
-	unsigned int pd =  (pll >> 26) & 0xf;
-
-	mfi = mfi <= 5 ? 5 : mfi;
-
-	return lldiv(2 * (u64)f_ref * (mfi * (mfd + 1) + mfn),
-			(mfd + 1) * (pd + 1));
-}
-
-static ulong clk_in_32k(void)
-{
-	return 1024 * CONFIG_MX27_CLK32;
-}
-
-static ulong clk_in_26m(void)
-{
-	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
-
-	if (readl(&pll->cscr) & CSCR_OSC26M_DIV1P5) {
-		/* divide by 1.5 */
-		return 26000000 * 2 / 3;
-	} else {
-		return 26000000;
-	}
-}
-
-ulong imx_get_mpllclk(void)
-{
-	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
-	ulong cscr = readl(&pll->cscr);
-	ulong fref;
-
-	if (cscr & CSCR_MCU_SEL)
-		fref = clk_in_26m();
-	else
-		fref = clk_in_32k();
-
-	return imx_decode_pll(readl(&pll->mpctl0), fref);
-}
-
-ulong imx_get_armclk(void)
-{
-	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
-	ulong cscr = readl(&pll->cscr);
-	ulong fref = imx_get_mpllclk();
-	ulong div;
-
-	if (!(cscr & CSCR_ARM_SRC_MPLL))
-		fref = lldiv((fref * 2), 3);
-
-	div = ((cscr >> 12) & 0x3) + 1;
-
-	return lldiv(fref, div);
-}
-
-ulong imx_get_ahbclk(void)
-{
-	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
-	ulong cscr = readl(&pll->cscr);
-	ulong fref = imx_get_mpllclk();
-	ulong div;
-
-	div = ((cscr >> 8) & 0x3) + 1;
-
-	return lldiv(fref * 2, 3 * div);
-}
-
-ulong imx_get_spllclk(void)
-{
-	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
-	ulong cscr = readl(&pll->cscr);
-	ulong fref;
-
-	if (cscr & CSCR_SP_SEL)
-		fref = clk_in_26m();
-	else
-		fref = clk_in_32k();
-
-	return imx_decode_pll(readl(&pll->spctl0), fref);
-}
-
-static ulong imx_decode_perclk(ulong div)
-{
-	return lldiv((imx_get_mpllclk() * 2), (div * 3));
-}
-
-ulong imx_get_perclk1(void)
-{
-	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
-
-	return imx_decode_perclk((readl(&pll->pcdr1) & 0x3f) + 1);
-}
-
-ulong imx_get_perclk2(void)
-{
-	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
-
-	return imx_decode_perclk(((readl(&pll->pcdr1) >> 8) & 0x3f) + 1);
-}
-
-ulong imx_get_perclk3(void)
-{
-	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
-
-	return imx_decode_perclk(((readl(&pll->pcdr1) >> 16) & 0x3f) + 1);
-}
-
-ulong imx_get_perclk4(void)
-{
-	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
-
-	return imx_decode_perclk(((readl(&pll->pcdr1) >> 24) & 0x3f) + 1);
-}
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo (void)
-{
-	char buf[32];
-
-	printf("CPU:   Freescale i.MX27 at %s MHz\n\n",
-			strmhz(buf, imx_get_mpllclk()));
-	return 0;
-}
-#endif
-
-int cpu_eth_init(bd_t *bis)
-{
-#if defined(CONFIG_FEC_MXC)
-	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
-
-	/* enable FEC clock */
-	writel(readl(&pll->pccr1) | PCCR1_HCLK_FEC, &pll->pccr1);
-	writel(readl(&pll->pccr0) | PCCR0_FEC_EN, &pll->pccr0);
-	return fecmxc_initialize(bis);
-#else
-	return 0;
-#endif
-}
-
-/*
- * Initializes on-chip MMC controllers.
- * to override, implement board_mmc_init()
- */
-int cpu_mmc_init(bd_t *bis)
-{
-#ifdef CONFIG_MXC_MMC
-	return mxc_mmc_init(bis);
-#else
-	return 0;
-#endif
-}
-
-void imx_gpio_mode(int gpio_mode)
-{
-	struct gpio_regs *regs = (struct gpio_regs *)IMX_GPIO_BASE;
-	unsigned int pin = gpio_mode & GPIO_PIN_MASK;
-	unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
-	unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> GPIO_OCR_SHIFT;
-	unsigned int aout = (gpio_mode & GPIO_AOUT_MASK) >> GPIO_AOUT_SHIFT;
-	unsigned int bout = (gpio_mode & GPIO_BOUT_MASK) >> GPIO_BOUT_SHIFT;
-	unsigned int tmp;
-
-	/* Pullup enable */
-	if (gpio_mode & GPIO_PUEN) {
-		writel(readl(&regs->port[port].puen) | (1 << pin),
-				&regs->port[port].puen);
-	} else {
-		writel(readl(&regs->port[port].puen) & ~(1 << pin),
-				&regs->port[port].puen);
-	}
-
-	/* Data direction */
-	if (gpio_mode & GPIO_OUT) {
-		writel(readl(&regs->port[port].ddir) | 1 << pin,
-				&regs->port[port].ddir);
-	} else {
-		writel(readl(&regs->port[port].ddir) & ~(1 << pin),
-				&regs->port[port].ddir);
-	}
-
-	/* Primary / alternate function */
-	if (gpio_mode & GPIO_AF) {
-		writel(readl(&regs->port[port].gpr) | (1 << pin),
-				&regs->port[port].gpr);
-	} else {
-		writel(readl(&regs->port[port].gpr) & ~(1 << pin),
-				&regs->port[port].gpr);
-	}
-
-	/* use as gpio? */
-	if (!(gpio_mode & (GPIO_PF | GPIO_AF))) {
-		writel(readl(&regs->port[port].gius) | (1 << pin),
-				&regs->port[port].gius);
-	} else {
-		writel(readl(&regs->port[port].gius) & ~(1 << pin),
-				&regs->port[port].gius);
-	}
-
-	/* Output / input configuration */
-	if (pin < 16) {
-		tmp = readl(&regs->port[port].ocr1);
-		tmp &= ~(3 << (pin * 2));
-		tmp |= (ocr << (pin * 2));
-		writel(tmp, &regs->port[port].ocr1);
-
-		writel(readl(&regs->port[port].iconfa1) & ~(3 << (pin * 2)),
-				&regs->port[port].iconfa1);
-		writel(readl(&regs->port[port].iconfa1) | aout << (pin * 2),
-				&regs->port[port].iconfa1);
-		writel(readl(&regs->port[port].iconfb1) & ~(3 << (pin * 2)),
-				&regs->port[port].iconfb1);
-		writel(readl(&regs->port[port].iconfb1) | bout << (pin * 2),
-				&regs->port[port].iconfb1);
-	} else {
-		pin -= 16;
-
-		tmp = readl(&regs->port[port].ocr2);
-		tmp &= ~(3 << (pin * 2));
-		tmp |= (ocr << (pin * 2));
-		writel(tmp, &regs->port[port].ocr2);
-
-		writel(readl(&regs->port[port].iconfa2) & ~(3 << (pin * 2)),
-				&regs->port[port].iconfa2);
-		writel(readl(&regs->port[port].iconfa2) | aout << (pin * 2),
-				&regs->port[port].iconfa2);
-		writel(readl(&regs->port[port].iconfb2) & ~(3 << (pin * 2)),
-				&regs->port[port].iconfb2);
-		writel(readl(&regs->port[port].iconfb2) | bout << (pin * 2),
-				&regs->port[port].iconfb2);
-	}
-}
-
-#ifdef CONFIG_MXC_UART
-void mx27_uart_init_pins(void)
-{
-	int i;
-	unsigned int mode[] = {
-		PE12_PF_UART1_TXD,
-		PE13_PF_UART1_RXD,
-	};
-
-	for (i = 0; i < ARRAY_SIZE(mode); i++)
-		imx_gpio_mode(mode[i]);
-
-}
-#endif /* CONFIG_MXC_UART */
-
-#ifdef CONFIG_FEC_MXC
-void mx27_fec_init_pins(void)
-{
-	int i;
-	unsigned int mode[] = {
-		PD0_AIN_FEC_TXD0,
-		PD1_AIN_FEC_TXD1,
-		PD2_AIN_FEC_TXD2,
-		PD3_AIN_FEC_TXD3,
-		PD4_AOUT_FEC_RX_ER,
-		PD5_AOUT_FEC_RXD1,
-		PD6_AOUT_FEC_RXD2,
-		PD7_AOUT_FEC_RXD3,
-		PD8_AF_FEC_MDIO,
-		PD9_AIN_FEC_MDC | GPIO_PUEN,
-		PD10_AOUT_FEC_CRS,
-		PD11_AOUT_FEC_TX_CLK,
-		PD12_AOUT_FEC_RXD0,
-		PD13_AOUT_FEC_RX_DV,
-		PD14_AOUT_FEC_CLR,
-		PD15_AOUT_FEC_COL,
-		PD16_AIN_FEC_TX_ER,
-		PF23_AIN_FEC_TX_EN,
-	};
-
-	for (i = 0; i < ARRAY_SIZE(mode); i++)
-		imx_gpio_mode(mode[i]);
-}
-#endif /* CONFIG_FEC_MXC */
-
-#ifdef CONFIG_MXC_MMC
-void mx27_sd2_init_pins(void)
-{
-	int i;
-	unsigned int mode[] = {
-		PB4_PF_SD2_D0,
-		PB5_PF_SD2_D1,
-		PB6_PF_SD2_D2,
-		PB7_PF_SD2_D3,
-		PB8_PF_SD2_CMD,
-		PB9_PF_SD2_CLK,
-	};
-
-	for (i = 0; i < ARRAY_SIZE(mode); i++)
-		imx_gpio_mode(mode[i]);
-
-}
-#endif /* CONFIG_MXC_MMC */
diff --git a/cpu/arm926ejs/mx27/reset.c b/cpu/arm926ejs/mx27/reset.c
deleted file mode 100644
index 6c54eafd37..0000000000
--- a/cpu/arm926ejs/mx27/reset.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * (C) Copyright 2009
- * Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-
-/*
- * Reset the cpu by setting up the watchdog timer and let it time out
- */
-void reset_cpu (ulong ignored)
-{
-	struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE;
-	/* Disable watchdog and set Time-Out field to 0 */
-	writel(0x00000000, &regs->wcr);
-
-	/* Write Service Sequence */
-	writel(0x00005555, &regs->wsr);
-	writel(0x0000AAAA, &regs->wsr);
-
-	/* Enable watchdog */
-	writel(WCR_WDE, &regs->wcr);
-
-	while (1);
-	/*NOTREACHED*/
-}
diff --git a/cpu/arm926ejs/mx27/timer.c b/cpu/arm926ejs/mx27/timer.c
deleted file mode 100644
index 8f1d47bba7..0000000000
--- a/cpu/arm926ejs/mx27/timer.c
+++ /dev/null
@@ -1,190 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * (C) Copyright 2009
- * Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <div64.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-
-/* General purpose timers bitfields */
-#define GPTCR_SWR		(1 << 15)	/* Software reset	*/
-#define GPTCR_FRR		(1 << 8)	/* Freerun / restart	*/
-#define GPTCR_CLKSOURCE_32	(4 << 1)	/* Clock source		*/
-#define GPTCR_TEN		1		/* Timer enable		*/
-
-static ulong timestamp;
-static ulong lastinc;
-
-/*
- * "time" is measured in 1 / CONFIG_SYS_HZ seconds,
- * "tick" is internal timer period
- */
-#ifdef CONFIG_MX27_TIMER_HIGH_PRECISION
-/* ~0.4% error - measured with stop-watch on 100s boot-delay */
-static inline unsigned long long tick_to_time(unsigned long long tick)
-{
-	tick *= CONFIG_SYS_HZ;
-	do_div(tick, CONFIG_MX27_CLK32);
-	return tick;
-}
-
-static inline unsigned long long time_to_tick(unsigned long long time)
-{
-	time *= CONFIG_MX27_CLK32;
-	do_div(time, CONFIG_SYS_HZ);
-	return time;
-}
-
-static inline unsigned long long us_to_tick(unsigned long long us)
-{
-	us = us * CONFIG_MX27_CLK32 + 999999;
-	do_div(us, 1000000);
-	return us;
-}
-#else
-/* ~2% error */
-#define TICK_PER_TIME	((CONFIG_MX27_CLK32 + CONFIG_SYS_HZ / 2) / \
-		CONFIG_SYS_HZ)
-#define US_PER_TICK	(1000000 / CONFIG_MX27_CLK32)
-
-static inline unsigned long long tick_to_time(unsigned long long tick)
-{
-	do_div(tick, TICK_PER_TIME);
-	return tick;
-}
-
-static inline unsigned long long time_to_tick(unsigned long long time)
-{
-	return time * TICK_PER_TIME;
-}
-
-static inline unsigned long long us_to_tick(unsigned long long us)
-{
-	us += US_PER_TICK - 1;
-	do_div(us, US_PER_TICK);
-	return us;
-}
-#endif
-
-/* nothing really to do with interrupts, just starts up a counter. */
-/* The 32768Hz 32-bit timer overruns in 131072 seconds */
-int timer_init(void)
-{
-	int i;
-	struct gpt_regs *regs = (struct gpt_regs *)IMX_TIM1_BASE;
-	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
-
-	/* setup GP Timer 1 */
-	writel(GPTCR_SWR, &regs->gpt_tctl);
-
-	writel(readl(&pll->pccr0) | PCCR0_GPT1_EN, &pll->pccr0);
-	writel(readl(&pll->pccr1) | PCCR1_PERCLK1_EN, &pll->pccr1);
-
-	for (i = 0; i < 100; i++)
-		writel(0, &regs->gpt_tctl); /* We have no udelay by now */
-	writel(0, &regs->gpt_tprer); /* 32Khz */
-	/* Freerun Mode, PERCLK1 input */
-	writel(readl(&regs->gpt_tctl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR,
-			&regs->gpt_tctl);
-	writel(readl(&regs->gpt_tctl) | GPTCR_TEN, &regs->gpt_tctl);
-
-	return 0;
-}
-
-void reset_timer_masked(void)
-{
-	struct gpt_regs *regs = (struct gpt_regs *)IMX_TIM1_BASE;
-	/* reset time */
-	/* capture current incrementer value time */
-	lastinc = readl(&regs->gpt_tcn);
-	timestamp = 0; /* start "advancing" time stamp from 0 */
-}
-
-void reset_timer(void)
-{
-	reset_timer_masked();
-}
-
-unsigned long long get_ticks (void)
-{
-	struct gpt_regs *regs = (struct gpt_regs *)IMX_TIM1_BASE;
-	ulong now = readl(&regs->gpt_tcn); /* current tick value */
-
-	if (now >= lastinc) {
-		/*
-		 * normal mode (non roll)
-		 * move stamp forward with absolut diff ticks
-		 */
-		timestamp += (now - lastinc);
-	} else {
-		/* we have rollover of incrementer */
-		timestamp += (0xFFFFFFFF - lastinc) + now;
-	}
-	lastinc = now;
-	return timestamp;
-}
-
-ulong get_timer_masked (void)
-{
-	/*
-	 * get_ticks() returns a long long (64 bit), it wraps in
-	 * 2^64 / CONFIG_MX27_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
-	 * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
-	 * 5 * 10^6 days - long enough.
-	 */
-	return tick_to_time(get_ticks());
-}
-
-ulong get_timer (ulong base)
-{
-	return get_timer_masked () - base;
-}
-
-void set_timer (ulong t)
-{
-	timestamp = time_to_tick(t);
-}
-
-/* delay x useconds AND preserve advance timstamp value */
-void __udelay (unsigned long usec)
-{
-	unsigned long long tmp;
-	ulong tmo;
-
-	tmo = us_to_tick(usec);
-	tmp = get_ticks() + tmo;	/* get current timestamp */
-
-	while (get_ticks() < tmp)	/* loop till event */
-		 /*NOP*/;
-}
diff --git a/cpu/arm926ejs/nomadik/Makefile b/cpu/arm926ejs/nomadik/Makefile
deleted file mode 100644
index 0fc9f2a4c1..0000000000
--- a/cpu/arm926ejs/nomadik/Makefile
+++ /dev/null
@@ -1,46 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).a
-
-COBJS	= timer.o gpio.o
-SOBJS	= reset.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS)) $(addprefix $(obj),$(SOBJS))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS)
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/cpu/arm926ejs/nomadik/gpio.c b/cpu/arm926ejs/nomadik/gpio.c
deleted file mode 100644
index 62a375b5b5..0000000000
--- a/cpu/arm926ejs/nomadik/gpio.c
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * (C) Copyright 2009 Alessandro Rubini
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/gpio.h>
-
-static unsigned long gpio_base[4] = {
-	NOMADIK_GPIO0_BASE,
-	NOMADIK_GPIO1_BASE,
-	NOMADIK_GPIO2_BASE,
-	NOMADIK_GPIO3_BASE
-};
-
-enum gpio_registers {
-	GPIO_DAT =	0x00,		/* data register */
-	GPIO_DATS =	0x04,		/* data set */
-	GPIO_DATC =	0x08,		/* data clear */
-	GPIO_PDIS =	0x0c,		/* pull disable */
-	GPIO_DIR =	0x10,		/* direction */
-	GPIO_DIRS =	0x14,		/* direction set */
-	GPIO_DIRC =	0x18,		/* direction clear */
-	GPIO_AFSLA =	0x20,		/* alternate function select A */
-	GPIO_AFSLB =	0x24,		/* alternate function select B */
-};
-
-static inline unsigned long gpio_to_base(int gpio)
-{
-	return gpio_base[gpio / 32];
-}
-
-static inline u32 gpio_to_bit(int gpio)
-{
-	return 1 << (gpio & 0x1f);
-}
-
-void nmk_gpio_af(int gpio, int alternate_function)
-{
-	unsigned long base = gpio_to_base(gpio);
-	u32 bit = gpio_to_bit(gpio);
-	u32 afunc, bfunc;
-
-	/* alternate function is 0..3, with one bit per register */
-	afunc = readl(base + GPIO_AFSLA) & ~bit;
-	bfunc = readl(base + GPIO_AFSLB) & ~bit;
-	if (alternate_function & 1) afunc |= bit;
-	if (alternate_function & 2) bfunc |= bit;
-	writel(afunc, base + GPIO_AFSLA);
-	writel(bfunc, base + GPIO_AFSLB);
-}
-
-void nmk_gpio_dir(int gpio, int dir)
-{
-	unsigned long base = gpio_to_base(gpio);
-	u32 bit = gpio_to_bit(gpio);
-
-	if (dir)
-		writel(bit, base + GPIO_DIRS);
-	else
-		writel(bit, base + GPIO_DIRC);
-}
-
-void nmk_gpio_set(int gpio, int val)
-{
-	unsigned long base = gpio_to_base(gpio);
-	u32 bit = gpio_to_bit(gpio);
-
-	if (val)
-		writel(bit, base + GPIO_DATS);
-	else
-		writel(bit, base + GPIO_DATC);
-}
-
-int nmk_gpio_get(int gpio)
-{
-	unsigned long base = gpio_to_base(gpio);
-	u32 bit = gpio_to_bit(gpio);
-
-	return readl(base + GPIO_DAT) & bit;
-}
diff --git a/cpu/arm926ejs/nomadik/reset.S b/cpu/arm926ejs/nomadik/reset.S
deleted file mode 100644
index ec954726ae..0000000000
--- a/cpu/arm926ejs/nomadik/reset.S
+++ /dev/null
@@ -1,14 +0,0 @@
-#include <config.h>
-/*
- * Processor reset for Nomadik
- */
-
-	.align 5
-.globl reset_cpu
-reset_cpu:
-	ldr	r0, =NOMADIK_SRC_BASE	/* System and Reset Controller */
-	ldr	r1, =0x1
-	str	r1, [r0, #0x18]
-
-_loop_forever:
-	b	_loop_forever
diff --git a/cpu/arm926ejs/nomadik/timer.c b/cpu/arm926ejs/nomadik/timer.c
deleted file mode 100644
index 1d98ef3eb3..0000000000
--- a/cpu/arm926ejs/nomadik/timer.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * (C) Copyright 2009 Alessandro Rubini
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/mtu.h>
-
-/*
- * The timer is a decrementer, we'll left it free running at 2.4MHz.
- * We have 2.4 ticks per microsecond and an overflow in almost 30min
- */
-#define TIMER_CLOCK		(24 * 100 * 1000)
-#define COUNT_TO_USEC(x)	((x) * 5 / 12)	/* overflows at 6min */
-#define USEC_TO_COUNT(x)	((x) * 12 / 5)	/* overflows at 6min */
-#define TICKS_PER_HZ		(TIMER_CLOCK / CONFIG_SYS_HZ)
-#define TICKS_TO_HZ(x)		((x) / TICKS_PER_HZ)
-
-/* macro to read the decrementing 32 bit timer as an increasing count */
-#define READ_TIMER() (0 - readl(CONFIG_SYS_TIMERBASE + MTU_VAL(0)))
-
-/* Configure a free-running, auto-wrap counter with no prescaler */
-int timer_init(void)
-{
-	writel(MTU_CRn_ENA | MTU_CRn_PRESCALE_1 | MTU_CRn_32BITS,
-	       CONFIG_SYS_TIMERBASE + MTU_CR(0));
-	reset_timer();
-	return 0;
-}
-
-/* Restart counting from 0 */
-void reset_timer(void)
-{
-	ulong val;
-	writel(0, CONFIG_SYS_TIMERBASE + MTU_LR(0));
-	/*
-	 * The load-register isn't really immediate: it changes on clock
-	 * edges, so we must wait for our newly-written value to appear.
-	 * Since we might miss reading 0, wait for any change in value.
-	 */
-	val = READ_TIMER();
-	while (READ_TIMER() == val)
-		;
-}
-
-/* Return how many HZ passed since "base" */
-ulong get_timer(ulong base)
-{
-	return  TICKS_TO_HZ(READ_TIMER()) - base;
-}
-
-/* Delay x useconds */
-void __udelay(unsigned long usec)
-{
-	ulong ini, end;
-
-	ini = READ_TIMER();
-	end = ini + USEC_TO_COUNT(usec);
-	while ((signed)(end - READ_TIMER()) > 0)
-		;
-}
diff --git a/cpu/arm926ejs/omap/Makefile b/cpu/arm926ejs/omap/Makefile
deleted file mode 100644
index 74aea74189..0000000000
--- a/cpu/arm926ejs/omap/Makefile
+++ /dev/null
@@ -1,47 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).a
-
-COBJS	= timer.o cpuinfo.o
-SOBJS	= reset.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS)
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/cpu/arm926ejs/omap/cpuinfo.c b/cpu/arm926ejs/omap/cpuinfo.c
deleted file mode 100644
index 0052daba8e..0000000000
--- a/cpu/arm926ejs/omap/cpuinfo.c
+++ /dev/null
@@ -1,241 +0,0 @@
-/*
- * OMAP1 CPU identification code
- *
- * Copyright (C) 2004 Nokia Corporation
- * Written by Tony Lindgren <tony@atomide.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <common.h>
-#include <command.h>
-
-#if defined(CONFIG_DISPLAY_CPUINFO) && defined(CONFIG_OMAP)
-
-#define omap_readw(x)		*(volatile unsigned short *)(x)
-#define omap_readl(x)		*(volatile unsigned long *)(x)
-
-#define OMAP_DIE_ID_0		0xfffe1800
-#define OMAP_DIE_ID_1		0xfffe1804
-#define OMAP_PRODUCTION_ID_0	0xfffe2000
-#define OMAP_PRODUCTION_ID_1	0xfffe2004
-#define OMAP32_ID_0		0xfffed400
-#define OMAP32_ID_1		0xfffed404
-
-struct omap_id {
-	u16	jtag_id;	/* Used to determine OMAP type */
-	u8	die_rev;	/* Processor revision */
-	u32	omap_id;	/* OMAP revision */
-	u32	type;		/* Cpu id bits [31:08], cpu class bits [07:00] */
-};
-
-/* Register values to detect the OMAP version */
-static struct omap_id omap_ids[] = {
-	{ .jtag_id = 0xb574, .die_rev = 0x2, .omap_id = 0x03310315, .type = 0x03100000},
-	{ .jtag_id = 0x355f, .die_rev = 0x0, .omap_id = 0x03320000, .type = 0x07300100},
-	{ .jtag_id = 0xb55f, .die_rev = 0x0, .omap_id = 0x03320000, .type = 0x07300300},
-	{ .jtag_id = 0xb470, .die_rev = 0x0, .omap_id = 0x03310100, .type = 0x15100000},
-	{ .jtag_id = 0xb576, .die_rev = 0x0, .omap_id = 0x03320000, .type = 0x16100000},
-	{ .jtag_id = 0xb576, .die_rev = 0x2, .omap_id = 0x03320100, .type = 0x16110000},
-	{ .jtag_id = 0xb576, .die_rev = 0x3, .omap_id = 0x03320100, .type = 0x16100c00},
-	{ .jtag_id = 0xb576, .die_rev = 0x0, .omap_id = 0x03320200, .type = 0x16100d00},
-	{ .jtag_id = 0xb613, .die_rev = 0x0, .omap_id = 0x03320300, .type = 0x1610ef00},
-	{ .jtag_id = 0xb613, .die_rev = 0x0, .omap_id = 0x03320300, .type = 0x1610ef00},
-	{ .jtag_id = 0xb576, .die_rev = 0x1, .omap_id = 0x03320100, .type = 0x16110000},
-	{ .jtag_id = 0xb58c, .die_rev = 0x2, .omap_id = 0x03320200, .type = 0x16110b00},
-	{ .jtag_id = 0xb58c, .die_rev = 0x3, .omap_id = 0x03320200, .type = 0x16110c00},
-	{ .jtag_id = 0xb65f, .die_rev = 0x0, .omap_id = 0x03320400, .type = 0x16212300},
-	{ .jtag_id = 0xb65f, .die_rev = 0x1, .omap_id = 0x03320400, .type = 0x16212300},
-	{ .jtag_id = 0xb65f, .die_rev = 0x1, .omap_id = 0x03320500, .type = 0x16212300},
-	{ .jtag_id = 0xb5f7, .die_rev = 0x0, .omap_id = 0x03330000, .type = 0x17100000},
-	{ .jtag_id = 0xb5f7, .die_rev = 0x1, .omap_id = 0x03330100, .type = 0x17100000},
-	{ .jtag_id = 0xb5f7, .die_rev = 0x2, .omap_id = 0x03330100, .type = 0x17100000},
-};
-
-/*
- * Get OMAP type from PROD_ID.
- * 1710 has the PROD_ID in bits 15:00, not in 16:01 as documented in TRM.
- * 1510 PROD_ID is empty, and 1610 PROD_ID does not make sense.
- * Undocumented register in TEST BLOCK is used as fallback; This seems to
- * work on 1510, 1610 & 1710. The official way hopefully will work in future
- * processors.
- */
-static u16 omap_get_jtag_id(void)
-{
-	u32 prod_id, omap_id;
-
-	prod_id = omap_readl(OMAP_PRODUCTION_ID_1);
-	omap_id = omap_readl(OMAP32_ID_1);
-
-	/* Check for unusable OMAP_PRODUCTION_ID_1 on 1611B/5912 and 730 */
-	if (((prod_id >> 20) == 0) || (prod_id == omap_id))
-		prod_id = 0;
-	else
-		prod_id &= 0xffff;
-
-	if (prod_id)
-		return prod_id;
-
-	/* Use OMAP32_ID_1 as fallback */
-	prod_id = ((omap_id >> 12) & 0xffff);
-
-	return prod_id;
-}
-
-/*
- * Get OMAP revision from DIE_REV.
- * Early 1710 processors may have broken OMAP_DIE_ID, it contains PROD_ID.
- * Undocumented register in the TEST BLOCK is used as fallback.
- * REVISIT: This does not seem to work on 1510
- */
-static u8 omap_get_die_rev(void)
-{
-	u32 die_rev;
-
-	die_rev = omap_readl(OMAP_DIE_ID_1);
-
-	/* Check for broken OMAP_DIE_ID on early 1710 */
-	if (((die_rev >> 12) & 0xffff) == omap_get_jtag_id())
-		die_rev = 0;
-
-	die_rev = (die_rev >> 17) & 0xf;
-	if (die_rev)
-		return die_rev;
-
-	die_rev = (omap_readl(OMAP32_ID_1) >> 28) & 0xf;
-
-	return die_rev;
-}
-
-static unsigned long dpll1(void)
-{
-	unsigned short pll_ctl_val = omap_readw(DPLL_CTL_REG);
-	unsigned long rate;
-
-	rate = CONFIG_SYS_CLK_FREQ; /* Base xtal rate */
-	if (pll_ctl_val & 0x10) {
-		/* PLL enabled, apply multiplier and divisor */
-		if (pll_ctl_val & 0xf80)
-			rate *= (pll_ctl_val & 0xf80) >> 7;
-		rate /= ((pll_ctl_val & 0x60) >> 5) + 1;
-	} else {
-		/* PLL disabled, apply bypass divisor */
-		switch (pll_ctl_val & 0xc) {
-		case 0:
-			break;
-		case 0x4:
-			rate /= 2;
-			break;
-		default:
-			rate /= 4;
-			break;
-		}
-	}
-
-	return rate;
-}
-
-static unsigned long armcore(void)
-{
-	unsigned short arm_ckctl = omap_readw(ARM_CKCTL);
-
-	return (dpll1() >> ((arm_ckctl & 0x0030) >> 4));
-}
-
-int print_cpuinfo (void)
-{
-	int i;
-	u16 jtag_id;
-	u8 die_rev;
-	u32 omap_id;
-	u8 cpu_type;
-	u32 system_serial_high;
-	u32 system_serial_low;
-	u32 system_rev = 0;
-
-	jtag_id = omap_get_jtag_id();
-	die_rev = omap_get_die_rev();
-	omap_id = omap_readl(OMAP32_ID_0);
-
-#ifdef DEBUG
-	printf("OMAP_DIE_ID_0: 0x%08x\n", omap_readl(OMAP_DIE_ID_0));
-	printf("OMAP_DIE_ID_1: 0x%08x DIE_REV: %i\n",
-	       omap_readl(OMAP_DIE_ID_1),
-	       (omap_readl(OMAP_DIE_ID_1) >> 17) & 0xf);
-	printf("OMAP_PRODUCTION_ID_0: 0x%08x\n", omap_readl(OMAP_PRODUCTION_ID_0));
-	printf("OMAP_PRODUCTION_ID_1: 0x%08x JTAG_ID: 0x%04x\n",
-	       omap_readl(OMAP_PRODUCTION_ID_1),
-	       omap_readl(OMAP_PRODUCTION_ID_1) & 0xffff);
-	printf("OMAP32_ID_0: 0x%08x\n", omap_readl(OMAP32_ID_0));
-	printf("OMAP32_ID_1: 0x%08x\n", omap_readl(OMAP32_ID_1));
-	printf("JTAG_ID: 0x%04x DIE_REV: %i\n", jtag_id, die_rev);
-#endif
-
-	system_serial_high = omap_readl(OMAP_DIE_ID_0);
-	system_serial_low = omap_readl(OMAP_DIE_ID_1);
-
-	/* First check only the major version in a safe way */
-	for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
-		if (jtag_id == (omap_ids[i].jtag_id)) {
-			system_rev = omap_ids[i].type;
-			break;
-		}
-	}
-
-	/* Check if we can find the die revision */
-	for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
-		if (jtag_id == omap_ids[i].jtag_id && die_rev == omap_ids[i].die_rev) {
-			system_rev = omap_ids[i].type;
-			break;
-		}
-	}
-
-	/* Finally check also the omap_id */
-	for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
-		if (jtag_id == omap_ids[i].jtag_id
-		    && die_rev == omap_ids[i].die_rev
-		    && omap_id == omap_ids[i].omap_id) {
-			system_rev = omap_ids[i].type;
-			break;
-		}
-	}
-
-	/* Add the cpu class info (7xx, 15xx, 16xx, 24xx) */
-	cpu_type = system_rev >> 24;
-
-	switch (cpu_type) {
-	case 0x07:
-		system_rev |= 0x07;
-		break;
-	case 0x03:
-	case 0x15:
-		system_rev |= 0x15;
-		break;
-	case 0x16:
-	case 0x17:
-		system_rev |= 0x16;
-		break;
-	case 0x24:
-		system_rev |= 0x24;
-		break;
-	default:
-		printf("Unknown OMAP cpu type: 0x%02x\n", cpu_type);
-	}
-
-	printf("CPU:   OMAP%04x", system_rev >> 16);
-	if ((system_rev >> 8) & 0xff)
-		printf("%x", (system_rev >> 8) & 0xff);
-#ifdef DEBUG
-	printf(" revision %i handled as %02xxx id: %08x%08x",
-	       die_rev, system_rev & 0xff, system_serial_low, system_serial_high);
-#endif
-	printf(" at %ld.%01ld MHz (DPLL1=%ld.%01ld MHz)\n",
-	       armcore() / 1000000, (armcore() / 100000) % 10,
-	       dpll1() / 1000000, (dpll1() / 100000) % 10);
-
-	return 0;
-}
-
-#endif /* #if defined(CONFIG_DISPLAY_CPUINFO) && defined(CONFIG_OMAP) */
diff --git a/cpu/arm926ejs/omap/reset.S b/cpu/arm926ejs/omap/reset.S
deleted file mode 100644
index 4b20756d1b..0000000000
--- a/cpu/arm926ejs/omap/reset.S
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- *  armboot - Startup Code for ARM926EJS CPU-core
- *
- *  Copyright (c) 2003  Texas Instruments
- *
- *  ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
- *
- *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
- *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
- *  Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
- *  Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
- *  Copyright (c) 2003	Kshitij <kshitij@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-	.align	5
-.globl reset_cpu
-reset_cpu:
-	ldr	r1, rstctl1	/* get clkm1 reset ctl */
-	mov	r3, #0x0
-	strh	r3, [r1]	/* clear it */
-	mov	r3, #0x8
-	strh	r3, [r1]	/* force dsp+arm reset */
-_loop_forever:
-	b	_loop_forever
-
-rstctl1:
-	.word	0xfffece10
diff --git a/cpu/arm926ejs/omap/timer.c b/cpu/arm926ejs/omap/timer.c
deleted file mode 100644
index 2ac38c40b7..0000000000
--- a/cpu/arm926ejs/omap/timer.c
+++ /dev/null
@@ -1,176 +0,0 @@
-/*
- * (C) Copyright 2003
- * Texas Instruments <www.ti.com>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002-2004
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * (C) Copyright 2004
- * Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-
-#define TIMER_LOAD_VAL 0xffffffff
-
-/* macro to read the 32 bit timer */
-#define READ_TIMER (*(volatile ulong *)(CONFIG_SYS_TIMERBASE+8))
-
-static ulong timestamp;
-static ulong lastdec;
-
-int timer_init (void)
-{
-	int32_t val;
-
-	/* Start the decrementer ticking down from 0xffffffff */
-	*((int32_t *) (CONFIG_SYS_TIMERBASE + LOAD_TIM)) = TIMER_LOAD_VAL;
-	val = MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE | (CONFIG_SYS_PTV << MPUTIM_PTV_BIT);
-	*((int32_t *) (CONFIG_SYS_TIMERBASE + CNTL_TIMER)) = val;
-
-	/* init the timestamp and lastdec value */
-	reset_timer_masked();
-
-	return 0;
-}
-
-/*
- * timer without interrupts
- */
-
-void reset_timer (void)
-{
-	reset_timer_masked ();
-}
-
-ulong get_timer (ulong base)
-{
-	return get_timer_masked () - base;
-}
-
-void set_timer (ulong t)
-{
-	timestamp = t;
-}
-
-/* delay x useconds AND perserve advance timstamp value */
-void __udelay (unsigned long usec)
-{
-	ulong tmo, tmp;
-
-	if(usec >= 1000){		/* if "big" number, spread normalization to seconds */
-		tmo = usec / 1000;	/* start to normalize for usec to ticks per sec */
-		tmo *= CONFIG_SYS_HZ;		/* find number of "ticks" to wait to achieve target */
-		tmo /= 1000;		/* finish normalize. */
-	}else{				/* else small number, don't kill it prior to HZ multiply */
-		tmo = usec * CONFIG_SYS_HZ;
-		tmo /= (1000*1000);
-	}
-
-	tmp = get_timer (0);		/* get current timestamp */
-	if( (tmo + tmp + 1) < tmp )	/* if setting this fordward will roll time stamp */
-		reset_timer_masked ();	/* reset "advancing" timestamp to 0, set lastdec value */
-	else
-		tmo += tmp;		/* else, set advancing stamp wake up time */
-
-	while (get_timer_masked () < tmo)/* loop till event */
-		/*NOP*/;
-}
-
-void reset_timer_masked (void)
-{
-	/* reset time */
-	lastdec = READ_TIMER;  /* capure current decrementer value time */
-	timestamp = 0;	       /* start "advancing" time stamp from 0 */
-}
-
-ulong get_timer_masked (void)
-{
-	ulong now = READ_TIMER;		/* current tick value */
-
-	if (lastdec >= now) {		/* normal mode (non roll) */
-		/* normal mode */
-		timestamp += lastdec - now; /* move stamp fordward with absoulte diff ticks */
-	} else {			/* we have overflow of the count down timer */
-		/* nts = ts + ld + (TLV - now)
-		 * ts=old stamp, ld=time that passed before passing through -1
-		 * (TLV-now) amount of time after passing though -1
-		 * nts = new "advancing time stamp"...it could also roll and cause problems.
-		 */
-		timestamp += lastdec + TIMER_LOAD_VAL - now;
-	}
-	lastdec = now;
-
-	return timestamp;
-}
-
-/* waits specified delay value and resets timestamp */
-void udelay_masked (unsigned long usec)
-{
-	ulong tmo;
-	ulong endtime;
-	signed long diff;
-
-	if (usec >= 1000) {		/* if "big" number, spread normalization to seconds */
-		tmo = usec / 1000;	/* start to normalize for usec to ticks per sec */
-		tmo *= CONFIG_SYS_HZ;		/* find number of "ticks" to wait to achieve target */
-		tmo /= 1000;		/* finish normalize. */
-	} else {			/* else small number, don't kill it prior to HZ multiply */
-		tmo = usec * CONFIG_SYS_HZ;
-		tmo /= (1000*1000);
-	}
-
-	endtime = get_timer_masked () + tmo;
-
-	do {
-		ulong now = get_timer_masked ();
-		diff = endtime - now;
-	} while (diff >= 0);
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-	return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk (void)
-{
-	ulong tbclk;
-
-	tbclk = CONFIG_SYS_HZ;
-	return tbclk;
-}
diff --git a/cpu/arm926ejs/spear/Makefile b/cpu/arm926ejs/spear/Makefile
deleted file mode 100644
index bf8dfa8c3c..0000000000
--- a/cpu/arm926ejs/spear/Makefile
+++ /dev/null
@@ -1,52 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).a
-
-COBJS	:= reset.o \
-	   timer.o
-SOBJS	:=
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
-
-clean:
-	rm -f $(SOBJS) $(OBJS)
-
-distclean:	clean
-	rm -f $(LIB) core *.bak $(obj).depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/cpu/arm926ejs/spear/reset.c b/cpu/arm926ejs/spear/reset.c
deleted file mode 100644
index 73ad86da30..0000000000
--- a/cpu/arm926ejs/spear/reset.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * (C) Copyright 2009
- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/spr_syscntl.h>
-
-void reset_cpu(ulong ignored)
-{
-	struct syscntl_regs *syscntl_regs_p =
-	    (struct syscntl_regs *)CONFIG_SPEAR_SYSCNTLBASE;
-
-	printf("System is going to reboot ...\n");
-
-	/*
-	 * This 1 second delay will allow the above message
-	 * to be printed before reset
-	 */
-	udelay((1000 * 1000));
-
-	/* Going into slow mode before resetting SOC */
-	writel(0x02, &syscntl_regs_p->scctrl);
-
-	/*
-	 * Writing any value to the system status register will
-	 * reset the SoC
-	 */
-	writel(0x00, &syscntl_regs_p->scsysstat);
-
-	/* system will restart */
-	while (1)
-		;
-}
diff --git a/cpu/arm926ejs/spear/timer.c b/cpu/arm926ejs/spear/timer.c
deleted file mode 100644
index 06858b4a13..0000000000
--- a/cpu/arm926ejs/spear/timer.c
+++ /dev/null
@@ -1,153 +0,0 @@
-/*
- * (C) Copyright 2009
- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/spr_gpt.h>
-#include <asm/arch/spr_misc.h>
-
-#define GPT_RESOLUTION	(CONFIG_SPEAR_HZ_CLOCK / CONFIG_SPEAR_HZ)
-#define READ_TIMER()	(readl(&gpt_regs_p->count) & GPT_FREE_RUNNING)
-
-static struct gpt_regs *const gpt_regs_p =
-    (struct gpt_regs *)CONFIG_SPEAR_TIMERBASE;
-
-static struct misc_regs *const misc_regs_p =
-    (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
-
-static ulong timestamp;
-static ulong lastdec;
-
-int timer_init(void)
-{
-	u32 synth;
-
-	/* Prescaler setting */
-#if defined(CONFIG_SPEAR3XX)
-	writel(MISC_PRSC_CFG, &misc_regs_p->prsc2_clk_cfg);
-	synth = MISC_GPT4SYNTH;
-#elif defined(CONFIG_SPEAR600)
-	writel(MISC_PRSC_CFG, &misc_regs_p->prsc1_clk_cfg);
-	synth = MISC_GPT3SYNTH;
-#else
-# error Incorrect config. Can only be spear{600|300|310|320}
-#endif
-
-	writel(readl(&misc_regs_p->periph_clk_cfg) | synth,
-	       &misc_regs_p->periph_clk_cfg);
-
-	/* disable timers */
-	writel(GPT_PRESCALER_1 | GPT_MODE_AUTO_RELOAD, &gpt_regs_p->control);
-
-	/* load value for free running */
-	writel(GPT_FREE_RUNNING, &gpt_regs_p->compare);
-
-	/* auto reload, start timer */
-	writel(readl(&gpt_regs_p->control) | GPT_ENABLE, &gpt_regs_p->control);
-
-	reset_timer_masked();
-
-	return 0;
-}
-
-/*
- * timer without interrupts
- */
-
-void reset_timer(void)
-{
-	reset_timer_masked();
-}
-
-ulong get_timer(ulong base)
-{
-	return (get_timer_masked() / GPT_RESOLUTION) - base;
-}
-
-void set_timer(ulong t)
-{
-	timestamp = t;
-}
-
-void __udelay(unsigned long usec)
-{
-	ulong tmo;
-	ulong start = get_timer_masked();
-	ulong tenudelcnt = CONFIG_SPEAR_HZ_CLOCK / (1000 * 100);
-	ulong rndoff;
-
-	rndoff = (usec % 10) ? 1 : 0;
-
-	/* tenudelcnt timer tick gives 10 microsecconds delay */
-	tmo = ((usec / 10) + rndoff) * tenudelcnt;
-
-	while ((ulong) (get_timer_masked() - start) < tmo)
-		;
-}
-
-void reset_timer_masked(void)
-{
-	/* reset time */
-	lastdec = READ_TIMER();
-	timestamp = 0;
-}
-
-ulong get_timer_masked(void)
-{
-	ulong now = READ_TIMER();
-
-	if (now >= lastdec) {
-		/* normal mode */
-		timestamp += now - lastdec;
-	} else {
-		/* we have an overflow ... */
-		timestamp += now + GPT_FREE_RUNNING - lastdec;
-	}
-	lastdec = now;
-
-	return timestamp;
-}
-
-void udelay_masked(unsigned long usec)
-{
-	return udelay(usec);
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-	return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
-	return CONFIG_SPEAR_HZ;
-}
diff --git a/cpu/arm926ejs/start.S b/cpu/arm926ejs/start.S
deleted file mode 100644
index 3b81151f49..0000000000
--- a/cpu/arm926ejs/start.S
+++ /dev/null
@@ -1,440 +0,0 @@
-/*
- *  armboot - Startup Code for ARM926EJS CPU-core
- *
- *  Copyright (c) 2003  Texas Instruments
- *
- *  ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
- *
- *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
- *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
- *  Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
- *  Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
- *  Copyright (c) 2003	Kshitij <kshitij@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-#include <config.h>
-#include <common.h>
-#include <version.h>
-
-#if defined(CONFIG_OMAP1610)
-#include <./configs/omap1510.h>
-#elif defined(CONFIG_OMAP730)
-#include <./configs/omap730.h>
-#endif
-
-/*
- *************************************************************************
- *
- * Jump vector table as in table 3.1 in [1]
- *
- *************************************************************************
- */
-
-
-.globl _start
-_start:
-	b	reset
-#ifdef CONFIG_PRELOADER
-/* No exception handlers in preloader */
-	ldr	pc, _hang
-	ldr	pc, _hang
-	ldr	pc, _hang
-	ldr	pc, _hang
-	ldr	pc, _hang
-	ldr	pc, _hang
-	ldr	pc, _hang
-
-_hang:
-	.word	do_hang
-/* pad to 64 byte boundary */
-	.word	0x12345678
-	.word	0x12345678
-	.word	0x12345678
-	.word	0x12345678
-	.word	0x12345678
-	.word	0x12345678
-	.word	0x12345678
-#else
-	ldr	pc, _undefined_instruction
-	ldr	pc, _software_interrupt
-	ldr	pc, _prefetch_abort
-	ldr	pc, _data_abort
-	ldr	pc, _not_used
-	ldr	pc, _irq
-	ldr	pc, _fiq
-
-_undefined_instruction:
-	.word undefined_instruction
-_software_interrupt:
-	.word software_interrupt
-_prefetch_abort:
-	.word prefetch_abort
-_data_abort:
-	.word data_abort
-_not_used:
-	.word not_used
-_irq:
-	.word irq
-_fiq:
-	.word fiq
-
-#endif	/* CONFIG_PRELOADER */
-	.balignl 16,0xdeadbeef
-
-
-/*
- *************************************************************************
- *
- * Startup Code (reset vector)
- *
- * do important init only if we don't start from memory!
- * setup Memory and board specific bits prior to relocation.
- * relocate armboot to ram
- * setup stack
- *
- *************************************************************************
- */
-
-_TEXT_BASE:
-	.word	TEXT_BASE
-
-.globl _armboot_start
-_armboot_start:
-	.word _start
-
-/*
- * These are defined in the board-specific linker script.
- */
-.globl _bss_start
-_bss_start:
-	.word __bss_start
-
-.globl _bss_end
-_bss_end:
-	.word _end
-
-#ifdef CONFIG_USE_IRQ
-/* IRQ stack memory (calculated at run-time) */
-.globl IRQ_STACK_START
-IRQ_STACK_START:
-	.word	0x0badc0de
-
-/* IRQ stack memory (calculated at run-time) */
-.globl FIQ_STACK_START
-FIQ_STACK_START:
-	.word 0x0badc0de
-#endif
-
-
-/*
- * the actual reset code
- */
-
-reset:
-	/*
-	 * set the cpu to SVC32 mode
-	 */
-	mrs	r0,cpsr
-	bic	r0,r0,#0x1f
-	orr	r0,r0,#0xd3
-	msr	cpsr,r0
-
-	/*
-	 * we do sys-critical inits only at reboot,
-	 * not when booting from ram!
-	 */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-	bl	cpu_init_crit
-#endif
-
-#ifndef CONFIG_SKIP_RELOCATE_UBOOT
-relocate:				/* relocate U-Boot to RAM	    */
-	adr	r0, _start		/* r0 <- current position of code   */
-	ldr	r1, _TEXT_BASE		/* test if we run from flash or RAM */
-	cmp     r0, r1                  /* don't reloc during debug         */
-	beq     stack_setup
-	ldr	r2, _armboot_start
-	ldr	r3, _bss_start
-	sub	r2, r3, r2		/* r2 <- size of armboot            */
-	add	r2, r0, r2		/* r2 <- source end address         */
-
-copy_loop:
-	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
-	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end addreee [r2]    */
-	ble	copy_loop
-#endif	/* CONFIG_SKIP_RELOCATE_UBOOT */
-
-	/* Set up the stack						    */
-stack_setup:
-	ldr	r0, _TEXT_BASE		/* upper 128 KiB: relocated uboot   */
-	sub	sp, r0, #128		/* leave 32 words for abort-stack   */
-#ifndef CONFIG_PRELOADER
-	sub	r0, r0, #CONFIG_SYS_MALLOC_LEN	/* malloc area                      */
-	sub	r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo                        */
-#ifdef CONFIG_USE_IRQ
-	sub	r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
-#endif
-#endif /* CONFIG_PRELOADER */
-	sub	sp, r0, #12		/* leave 3 words for abort-stack    */
-	bic	sp, r0, #7		/* 8-byte align stack for ABI compliance */
-
-clear_bss:
-	ldr	r0, _bss_start		/* find start of bss segment        */
-	ldr	r1, _bss_end		/* stop here                        */
-	mov	r2, #0x00000000		/* clear                            */
-
-#ifndef CONFIG_PRELOADER
-clbss_l:str	r2, [r0]		/* clear loop...                    */
-	add	r0, r0, #4
-	cmp	r0, r1
-	ble	clbss_l
-
-	bl coloured_LED_init
-	bl red_LED_on
-#endif /* CONFIG_PRELOADER */
-
-	ldr	pc, _start_armboot
-
-_start_armboot:
-#ifdef CONFIG_NAND_SPL
-	.word nand_boot
-#else
-	.word start_armboot
-#endif /* CONFIG_NAND_SPL */
-
-
-/*
- *************************************************************************
- *
- * CPU_init_critical registers
- *
- * setup important registers
- * setup memory timing
- *
- *************************************************************************
- */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-cpu_init_crit:
-	/*
-	 * flush v4 I/D caches
-	 */
-	mov	r0, #0
-	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
-	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */
-
-	/*
-	 * disable MMU stuff and caches
-	 */
-	mrc	p15, 0, r0, c1, c0, 0
-	bic	r0, r0, #0x00002300	/* clear bits 13, 9:8 (--V- --RS) */
-	bic	r0, r0, #0x00000087	/* clear bits 7, 2:0 (B--- -CAM) */
-	orr	r0, r0, #0x00000002	/* set bit 2 (A) Align */
-	orr	r0, r0, #0x00001000	/* set bit 12 (I) I-Cache */
-	mcr	p15, 0, r0, c1, c0, 0
-
-	/*
-	 * Go setup Memory and board specific bits prior to relocation.
-	 */
-	mov	ip, lr		/* perserve link reg across call */
-	bl	lowlevel_init	/* go setup pll,mux,memory */
-	mov	lr, ip		/* restore link */
-	mov	pc, lr		/* back to my caller */
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
-
-#ifndef CONFIG_PRELOADER
-/*
- *************************************************************************
- *
- * Interrupt handling
- *
- *************************************************************************
- */
-
-@
-@ IRQ stack frame.
-@
-#define S_FRAME_SIZE	72
-
-#define S_OLD_R0	68
-#define S_PSR		64
-#define S_PC		60
-#define S_LR		56
-#define S_SP		52
-
-#define S_IP		48
-#define S_FP		44
-#define S_R10		40
-#define S_R9		36
-#define S_R8		32
-#define S_R7		28
-#define S_R6		24
-#define S_R5		20
-#define S_R4		16
-#define S_R3		12
-#define S_R2		8
-#define S_R1		4
-#define S_R0		0
-
-#define MODE_SVC 0x13
-#define I_BIT	 0x80
-
-/*
- * use bad_save_user_regs for abort/prefetch/undef/swi ...
- * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
- */
-
-	.macro	bad_save_user_regs
-	@ carve out a frame on current user stack
-	sub	sp, sp, #S_FRAME_SIZE
-	stmia	sp, {r0 - r12}	@ Save user registers (now in svc mode) r0-r12
-
-	ldr	r2, _armboot_start
-	sub	r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
-	sub	r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8)  @ set base 2 words into abort stack
-	@ get values for "aborted" pc and cpsr (into parm regs)
-	ldmia	r2, {r2 - r3}
-	add	r0, sp, #S_FRAME_SIZE		@ grab pointer to old stack
-	add	r5, sp, #S_SP
-	mov	r1, lr
-	stmia	r5, {r0 - r3}	@ save sp_SVC, lr_SVC, pc, cpsr
-	mov	r0, sp		@ save current stack into r0 (param register)
-	.endm
-
-	.macro	irq_save_user_regs
-	sub	sp, sp, #S_FRAME_SIZE
-	stmia	sp, {r0 - r12}			@ Calling r0-r12
-	@ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
-	add	r8, sp, #S_PC
-	stmdb	r8, {sp, lr}^		@ Calling SP, LR
-	str	lr, [r8, #0]		@ Save calling PC
-	mrs	r6, spsr
-	str	r6, [r8, #4]		@ Save CPSR
-	str	r0, [r8, #8]		@ Save OLD_R0
-	mov	r0, sp
-	.endm
-
-	.macro	irq_restore_user_regs
-	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
-	mov	r0, r0
-	ldr	lr, [sp, #S_PC]			@ Get PC
-	add	sp, sp, #S_FRAME_SIZE
-	subs	pc, lr, #4		@ return & move spsr_svc into cpsr
-	.endm
-
-	.macro get_bad_stack
-	ldr	r13, _armboot_start		@ setup our mode stack
-	sub	r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
-	sub	r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
-
-	str	lr, [r13]	@ save caller lr in position 0 of saved stack
-	mrs	lr, spsr	@ get the spsr
-	str	lr, [r13, #4]	@ save spsr in position 1 of saved stack
-	mov	r13, #MODE_SVC	@ prepare SVC-Mode
-	@ msr	spsr_c, r13
-	msr	spsr, r13	@ switch modes, make sure moves will execute
-	mov	lr, pc		@ capture return pc
-	movs	pc, lr		@ jump to next instruction & switch modes.
-	.endm
-
-	.macro get_irq_stack			@ setup IRQ stack
-	ldr	sp, IRQ_STACK_START
-	.endm
-
-	.macro get_fiq_stack			@ setup FIQ stack
-	ldr	sp, FIQ_STACK_START
-	.endm
-#endif	/* CONFIG_PRELOADER */
-
-/*
- * exception handlers
- */
-#ifdef CONFIG_PRELOADER
-	.align	5
-do_hang:
-	ldr	sp, _TEXT_BASE			/* switch to abort stack */
-1:
-	bl	1b				/* hang and never return */
-#else	/* !CONFIG_PRELOADER */
-	.align  5
-undefined_instruction:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_undefined_instruction
-
-	.align	5
-software_interrupt:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_software_interrupt
-
-	.align	5
-prefetch_abort:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_prefetch_abort
-
-	.align	5
-data_abort:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_data_abort
-
-	.align	5
-not_used:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_not_used
-
-#ifdef CONFIG_USE_IRQ
-
-	.align	5
-irq:
-	get_irq_stack
-	irq_save_user_regs
-	bl	do_irq
-	irq_restore_user_regs
-
-	.align	5
-fiq:
-	get_fiq_stack
-	/* someone ought to write a more effiction fiq_save_user_regs */
-	irq_save_user_regs
-	bl	do_fiq
-	irq_restore_user_regs
-
-#else
-
-	.align	5
-irq:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_irq
-
-	.align	5
-fiq:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_fiq
-
-#endif
-#endif	/* CONFIG_PRELOADER */
diff --git a/cpu/arm926ejs/u-boot.lds b/cpu/arm926ejs/u-boot.lds
deleted file mode 100644
index ee5eeb590a..0000000000
--- a/cpu/arm926ejs/u-boot.lds
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * (C) Copyright 2002-2004
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(4);
-	.text :
-	{
-		cpu/arm926ejs/start.o	(.text)
-		*(.text)
-	}
-
-	. = ALIGN(4);
-	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
-	. = ALIGN(4);
-	.data : { *(.data) }
-
-	. = ALIGN(4);
-	.got : { *(.got) }
-
-	. = .;
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
-	__u_boot_cmd_end = .;
-
-	. = ALIGN(4);
-	__bss_start = .;
-	.bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
-	_end = .;
-}
diff --git a/cpu/arm926ejs/versatile/Makefile b/cpu/arm926ejs/versatile/Makefile
deleted file mode 100644
index c335d5c866..0000000000
--- a/cpu/arm926ejs/versatile/Makefile
+++ /dev/null
@@ -1,47 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).a
-
-COBJS	= timer.o
-SOBJS	= reset.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS)
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/cpu/arm926ejs/versatile/reset.S b/cpu/arm926ejs/versatile/reset.S
deleted file mode 100644
index 4b20756d1b..0000000000
--- a/cpu/arm926ejs/versatile/reset.S
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- *  armboot - Startup Code for ARM926EJS CPU-core
- *
- *  Copyright (c) 2003  Texas Instruments
- *
- *  ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
- *
- *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
- *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
- *  Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
- *  Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
- *  Copyright (c) 2003	Kshitij <kshitij@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-	.align	5
-.globl reset_cpu
-reset_cpu:
-	ldr	r1, rstctl1	/* get clkm1 reset ctl */
-	mov	r3, #0x0
-	strh	r3, [r1]	/* clear it */
-	mov	r3, #0x8
-	strh	r3, [r1]	/* force dsp+arm reset */
-_loop_forever:
-	b	_loop_forever
-
-rstctl1:
-	.word	0xfffece10
diff --git a/cpu/arm926ejs/versatile/timer.c b/cpu/arm926ejs/versatile/timer.c
deleted file mode 100644
index 563db36548..0000000000
--- a/cpu/arm926ejs/versatile/timer.c
+++ /dev/null
@@ -1,205 +0,0 @@
-/*
- * (C) Copyright 2003
- * Texas Instruments <www.ti.com>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002-2004
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * (C) Copyright 2004
- * Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-
-#define TIMER_LOAD_VAL 0xffffffff
-
-/* macro to read the 32 bit timer */
-#define READ_TIMER (*(volatile ulong *)(CONFIG_SYS_TIMERBASE+4))
-
-static ulong timestamp;
-static ulong lastdec;
-
-#define TIMER_ENABLE	(1 << 7)
-#define TIMER_MODE_MSK	(1 << 6)
-#define TIMER_MODE_FR	(0 << 6)
-#define TIMER_MODE_PD	(1 << 6)
-
-#define TIMER_INT_EN	(1 << 5)
-#define TIMER_PRS_MSK	(3 << 2)
-#define TIMER_PRS_8S	(1 << 3)
-#define TIMER_SIZE_MSK	(1 << 2)
-#define TIMER_ONE_SHT	(1 << 0)
-
-int timer_init (void)
-{
-	ulong	tmr_ctrl_val;
-
-	/* 1st disable the Timer */
-	tmr_ctrl_val = *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8);
-	tmr_ctrl_val &= ~TIMER_ENABLE;
-	*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = tmr_ctrl_val;
-
-	/*
-	 * The Timer Control Register has one Undefined/Shouldn't Use Bit
-	 * So we should do read/modify/write Operation
-	 */
-
-	/*
-	 * Timer Mode : Free Running
-	 * Interrupt : Disabled
-	 * Prescale : 8 Stage, Clk/256
-	 * Tmr Siz : 16 Bit Counter
-	 * Tmr in Wrapping Mode
-	 */
-	tmr_ctrl_val = *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8);
-	tmr_ctrl_val &= ~(TIMER_MODE_MSK | TIMER_INT_EN | TIMER_PRS_MSK | TIMER_SIZE_MSK | TIMER_ONE_SHT );
-	tmr_ctrl_val |= (TIMER_ENABLE | TIMER_PRS_8S);
-
-	*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = tmr_ctrl_val;
-
-	/* init the timestamp and lastdec value */
-	reset_timer_masked();
-
-	return 0;
-}
-
-/*
- * timer without interrupts
- */
-
-void reset_timer (void)
-{
-	reset_timer_masked ();
-}
-
-ulong get_timer (ulong base)
-{
-	return get_timer_masked () - base;
-}
-
-void set_timer (ulong t)
-{
-	timestamp = t;
-}
-
-/* delay x useconds AND perserve advance timstamp value */
-void __udelay (unsigned long usec)
-{
-	ulong tmo, tmp;
-
-	if(usec >= 1000){		/* if "big" number, spread normalization to seconds */
-		tmo = usec / 1000;	/* start to normalize for usec to ticks per sec */
-		tmo *= CONFIG_SYS_HZ;		/* find number of "ticks" to wait to achieve target */
-		tmo /= 1000;		/* finish normalize. */
-	}else{				/* else small number, don't kill it prior to HZ multiply */
-		tmo = usec * CONFIG_SYS_HZ;
-		tmo /= (1000*1000);
-	}
-
-	tmp = get_timer (0);		/* get current timestamp */
-	if( (tmo + tmp + 1) < tmp )	/* if setting this fordward will roll time stamp */
-		reset_timer_masked ();	/* reset "advancing" timestamp to 0, set lastdec value */
-	else
-		tmo += tmp;		/* else, set advancing stamp wake up time */
-
-	while (get_timer_masked () < tmo)/* loop till event */
-		/*NOP*/;
-}
-
-void reset_timer_masked (void)
-{
-	/* reset time */
-	lastdec = READ_TIMER;  /* capure current decrementer value time */
-	timestamp = 0;	       /* start "advancing" time stamp from 0 */
-}
-
-ulong get_timer_masked (void)
-{
-	ulong now = READ_TIMER;		/* current tick value */
-
-	if (lastdec >= now) {		/* normal mode (non roll) */
-		/* normal mode */
-		timestamp += lastdec - now; /* move stamp fordward with absoulte diff ticks */
-	} else {			/* we have overflow of the count down timer */
-		/* nts = ts + ld + (TLV - now)
-		 * ts=old stamp, ld=time that passed before passing through -1
-		 * (TLV-now) amount of time after passing though -1
-		 * nts = new "advancing time stamp"...it could also roll and cause problems.
-		 */
-		timestamp += lastdec + TIMER_LOAD_VAL - now;
-	}
-	lastdec = now;
-
-	return timestamp;
-}
-
-/* waits specified delay value and resets timestamp */
-void udelay_masked (unsigned long usec)
-{
-	ulong tmo;
-	ulong endtime;
-	signed long diff;
-
-	if (usec >= 1000) {		/* if "big" number, spread normalization to seconds */
-		tmo = usec / 1000;	/* start to normalize for usec to ticks per sec */
-		tmo *= CONFIG_SYS_HZ;		/* find number of "ticks" to wait to achieve target */
-		tmo /= 1000;		/* finish normalize. */
-	} else {			/* else small number, don't kill it prior to HZ multiply */
-		tmo = usec * CONFIG_SYS_HZ;
-		tmo /= (1000*1000);
-	}
-
-	endtime = get_timer_masked () + tmo;
-
-	do {
-		ulong now = get_timer_masked ();
-		diff = endtime - now;
-	} while (diff >= 0);
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-	return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk (void)
-{
-	ulong tbclk;
-
-	tbclk = CONFIG_SYS_HZ;
-	return tbclk;
-}