diff options
| author | Dirk Behme <dirk.behme@googlemail.com> | 2009-08-08 09:30:22 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2009-08-08 11:34:11 +0200 |
| commit | 894113529e3a04871544dde977d6d7adee05d3bf (patch) | |
| tree | 05ee42da46bcddfe455b45aa209c0291c961c66a /cpu/arm_cortexa8/omap3 | |
| parent | 97a099eaa48d5c762c4f73c52c3090c513b8b877 (diff) | |
omap3: replace all instances of gpmc config struct by one global
Signed-off-by: Matthias Ludwig <mludwig@ultratronik.de>
Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
Diffstat (limited to 'cpu/arm_cortexa8/omap3')
| -rw-r--r-- | cpu/arm_cortexa8/omap3/mem.c | 21 | ||||
| -rw-r--r-- | cpu/arm_cortexa8/omap3/sys_info.c | 3 |
2 files changed, 11 insertions, 13 deletions
diff --git a/cpu/arm_cortexa8/omap3/mem.c b/cpu/arm_cortexa8/omap3/mem.c index aa15f942bd..079c848701 100644 --- a/cpu/arm_cortexa8/omap3/mem.c +++ b/cpu/arm_cortexa8/omap3/mem.c @@ -41,6 +41,8 @@ unsigned int boot_flash_sec; unsigned int boot_flash_type; volatile unsigned int boot_flash_env_addr; +struct gpmc *gpmc_cfg; + #if defined(CONFIG_CMD_NAND) static u32 gpmc_m_nand[GPMC_MAX_REG] = { M_NAND_GPMC_CONFIG1, @@ -51,8 +53,6 @@ static u32 gpmc_m_nand[GPMC_MAX_REG] = { M_NAND_GPMC_CONFIG6, 0 }; -struct gpmc *gpmc_cfg; - #if defined(CONFIG_ENV_IS_IN_NAND) #define GPMC_CS 0 #else @@ -219,7 +219,7 @@ void gpmc_init(void) { /* putting a blanket check on GPMC based on ZeBu for now */ u32 *gpmc_config = NULL; - struct gpmc *gpmc_base = (struct gpmc *)GPMC_BASE; + gpmc_cfg = (struct gpmc *)GPMC_BASE; u32 base = 0; u32 size = 0; u32 f_off = CONFIG_SYS_MONITOR_LEN; @@ -227,27 +227,26 @@ void gpmc_init(void) u32 config = 0; /* global settings */ - writel(0, &gpmc_base->irqenable); /* isr's sources masked */ - writel(0, &gpmc_base->timeout_control);/* timeout disable */ + writel(0, &gpmc_cfg->irqenable); /* isr's sources masked */ + writel(0, &gpmc_cfg->timeout_control);/* timeout disable */ - config = readl(&gpmc_base->config); + config = readl(&gpmc_cfg->config); config &= (~0xf00); - writel(config, &gpmc_base->config); + writel(config, &gpmc_cfg->config); /* * Disable the GPMC0 config set by ROM code * It conflicts with our MPDB (both at 0x08000000) */ - writel(0, &gpmc_base->cs[0].config7); + writel(0, &gpmc_cfg->cs[0].config7); sdelay(1000); #if defined(CONFIG_CMD_NAND) /* CS 0 */ gpmc_config = gpmc_m_nand; - gpmc_cfg = gpmc_base; base = PISMO1_NAND_BASE; size = PISMO1_NAND_SIZE; - enable_gpmc_cs_config(gpmc_config, &gpmc_base->cs[0], base, size); + enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size); #if defined(CONFIG_ENV_IS_IN_NAND) f_off = SMNAND_ENV_OFFSET; f_sec = SZ_128K; @@ -263,7 +262,7 @@ void gpmc_init(void) gpmc_config = gpmc_onenand; base = PISMO1_ONEN_BASE; size = PISMO1_ONEN_SIZE; - enable_gpmc_cs_config(gpmc_config, &gpmc_base->cs[0], base, size); + enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size); #if defined(CONFIG_ENV_IS_IN_ONENAND) f_off = ONENAND_ENV_OFFSET; f_sec = SZ_128K; diff --git a/cpu/arm_cortexa8/omap3/sys_info.c b/cpu/arm_cortexa8/omap3/sys_info.c index e0e5153ae3..765aaf2b37 100644 --- a/cpu/arm_cortexa8/omap3/sys_info.c +++ b/cpu/arm_cortexa8/omap3/sys_info.c @@ -32,7 +32,6 @@ #include <i2c.h> extern omap3_sysinfo sysinfo; -static struct gpmc *gpmc_base = (struct gpmc *)GPMC_BASE; static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE; static struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; static char *rev_s[CPU_3XX_MAX_REV] = { @@ -160,7 +159,7 @@ u32 get_gpmc0_base(void) { u32 b; - b = readl(&gpmc_base->cs[0].config7); + b = readl(&gpmc_cfg->cs[0].config7); b &= 0x1F; /* keep base [5:0] */ b = b << 24; /* ret 0x0b000000 */ return b; |