diff options
| author | Dave Liu <daveliu@freescale.com> | 2009-03-14 12:48:30 +0800 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2009-03-30 13:33:50 -0500 |
| commit | c360ceac0286159f94d9d1a9496fc9858c8d9bec (patch) | |
| tree | fdd1868af478993fdb547171665c5c517ee6c071 /cpu/mpc85xx | |
| parent | 6a8197836702991468cead5ead073f589e2623ad (diff) | |
fsl-ddr: add the DDR3 SPD infrastructure
- support mirrored DIMMs, not support register DIMMs
- test passed on P2020DS board with MT9JSF12872AY-1G1D1
- test passed on MPC8569MDS board with MT8JSF12864HY-1G1D1
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Travis Wheatley <travis.wheatley@freescale.com>
Diffstat (limited to 'cpu/mpc85xx')
| -rw-r--r-- | cpu/mpc85xx/ddr-gen3.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/cpu/mpc85xx/ddr-gen3.c b/cpu/mpc85xx/ddr-gen3.c index 99c325a4ff..8ac3d5fbeb 100644 --- a/cpu/mpc85xx/ddr-gen3.c +++ b/cpu/mpc85xx/ddr-gen3.c @@ -98,10 +98,12 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, #endif /* - * 200 painful micro-seconds must elapse between + * 500 painful micro-seconds must elapse between * the DDR clock setup and the DDR config enable. + * DDR2 need 200 us, and DDR3 need 500 us from spec, + * we choose the max, that is 500 us for all of case. */ - udelay(200); + udelay(500); asm volatile("sync;isync"); /* Let the controller go */ |