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authorMarkus Klotzbuecher <mk@denx.de>2007-04-03 14:28:39 +0200
committerMarkus Klotzbuecher <mk@pollux.denx.de>2007-04-03 14:28:39 +0200
commit72c5e39c835f8257f8833411773902ce0e1ccbc3 (patch)
tree0f606c714e0f6988dc7552955c2f8d52ad867ac1 /cpu/mpc86xx/interrupts.c
parent822af351ad2babc7d99033361a5fcacd30f6bc78 (diff)
parent6db7d0af2336c126e4d4b2f248cc23516bdd46a8 (diff)
Merge with git://www.denx.de/git/u-boot.git
Diffstat (limited to 'cpu/mpc86xx/interrupts.c')
-rw-r--r--cpu/mpc86xx/interrupts.c20
1 files changed, 20 insertions, 0 deletions
diff --git a/cpu/mpc86xx/interrupts.c b/cpu/mpc86xx/interrupts.c
index 1df6cdc5b9..49820bbd81 100644
--- a/cpu/mpc86xx/interrupts.c
+++ b/cpu/mpc86xx/interrupts.c
@@ -80,6 +80,26 @@ int interrupt_init(void)
{
int ret;
+ /*
+ * The IRQ0 on Rev 2 is pulled high (low in Rev 1.x) to
+ * implement PEX10 errata. As INT is active high, it
+ * will cause core to take 0x500 interrupt.
+ *
+ * Due to the PIC's default pass through mode, as soon
+ * as interrupts are enabled (MSR[EE] = 1), an interrupt
+ * will be taken and u-boot will hang. This is due to a
+ * hardware change (per an errata fix) on new revisions
+ * of the board with Rev 2.x parts.
+ *
+ * Setting the PIC to mixed mode prevents the hang.
+ */
+ if ((get_svr() & 0xf0) == 0x20) {
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ immr->im_pic.gcr = MPC86xx_PICGCR_RST;
+ while (immr->im_pic.gcr & MPC86xx_PICGCR_RST);
+ immr->im_pic.gcr = MPC86xx_PICGCR_MODE;
+ }
+
/* call cpu specific function from $(CPU)/interrupts.c */
ret = interrupt_init_cpu(&decrementer_count);