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authorJens Gehrlein <jens.gehrlein@tqs.de>2007-09-26 17:55:54 +0200
committerWolfgang Denk <wd@denx.de>2007-12-27 01:59:50 +0100
commit22d1a56cbfb0bff34f477b4db6a55d076d829b83 (patch)
treeb8206a0016a00d0d13564b2ff22c080cadf9f762 /cpu/mpc8xx/speed.c
parentb988b8cd443989be65161888eea0127ad03f846f (diff)
TQM885D: Exchanged SDRAM timing by a more relaxed timing.
CAS-Latency=2, Write Recovery Time tWR=2 The max. supported bus frequency is 66 MHz. Therefore, changed threshold to switch from 1:1 mode to 2:1 from 80 MHz to 66 MHz. Signed-off-by: Martin Krause <martin.krause@tqs.de>
Diffstat (limited to 'cpu/mpc8xx/speed.c')
-rw-r--r--cpu/mpc8xx/speed.c5
1 files changed, 1 insertions, 4 deletions
diff --git a/cpu/mpc8xx/speed.c b/cpu/mpc8xx/speed.c
index 101d5f9cb3..11b089330b 100644
--- a/cpu/mpc8xx/speed.c
+++ b/cpu/mpc8xx/speed.c
@@ -259,11 +259,8 @@ int get_clocks_866 (void)
*/
sccr_reg = immr->im_clkrst.car_sccr;
sccr_reg &= ~SCCR_EBDF11;
-#if defined(CONFIG_TQM885D)
- if (gd->cpu_clk <= 80000000) {
-#else
+
if (gd->cpu_clk <= 66000000) {
-#endif
sccr_reg |= SCCR_EBDF00; /* bus division factor = 1 */
gd->bus_clk = gd->cpu_clk;
} else {