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authorKumar Gala <galak@kernel.crashing.org>2008-09-05 14:40:29 -0500
committerWolfgang Denk <wd@denx.de>2008-09-07 01:26:13 +0200
commit302e52e0b1d4c7f994991709d0cb6c3ea612cdb5 (patch)
tree8828ebe561992f114a67a31c89c4a601f9a96c16 /cpu/mpc8xxx/ddr/ctrl_regs.c
parentd1e2319414ea5218ba801163e4530ecf2dfcbf36 (diff)
Fix compiler warning in mpc8xxx ddr code
ctrl_regs.c: In function 'compute_fsl_memctl_config_regs': ctrl_regs.c:523: warning: 'caslat' may be used uninitialized in this function ctrl_regs.c:523: note: 'caslat' was declared here Add a warning in DDR1 case if cas_latency isn't a value we know about. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Diffstat (limited to 'cpu/mpc8xxx/ddr/ctrl_regs.c')
-rw-r--r--cpu/mpc8xxx/ddr/ctrl_regs.c6
1 files changed, 4 insertions, 2 deletions
diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c
index ca675512a2..e6c2a5ce7c 100644
--- a/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -520,7 +520,7 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
unsigned int wr; /* Write Recovery */
unsigned int dll_res; /* DLL Reset */
unsigned int mode; /* Normal=0 or Test=1 */
- unsigned int caslat; /* CAS# latency */
+ unsigned int caslat = 0;/* CAS# latency */
/* BT: Burst Type (0=Sequential, 1=Interleaved) */
unsigned int bt;
unsigned int bl; /* BL: Burst Length */
@@ -572,7 +572,9 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
0x6, /* 2.5 clocks */
0x3 /* 3.0 clocks */
};
- caslat = mode_caslat_table[cas_latency - 1];
+ caslat = mode_caslat_table[cas_latency - 1];
+ } else {
+ printf("Warning: unknown cas_latency %d\n", cas_latency);
}
#elif defined(CONFIG_FSL_DDR2)
caslat = cas_latency;