diff options
| author | Kumar Gala <galak@kernel.crashing.org> | 2009-06-11 23:42:35 -0500 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2009-06-12 09:15:50 -0500 |
| commit | e7563aff174f77aa61dab1ef5d9b47bebaa43702 (patch) | |
| tree | a3ef1e9c1745d417a06328e464446436dd46f2c7 /cpu/mpc8xxx/ddr/ddr1_dimm_params.c | |
| parent | d4b130dc80761b430dc5b410159cd158fca1a348 (diff) | |
fsl-ddr: Fix handling of >4G of memory when !CONFIG_PHYS_64BIT
The ddr code computes most things as 64-bit quantities and had some places
in the middle that it was using phy_addr_t and phys_size_t.
Instead we use unsigned long long through out and only at the last stage of
setting the LAWs and reporting the amount of memory to the board code do we
truncate down to what we can cover via phys_size_t.
This has the added benefit that the DDR controller itself is always setup
the same way regardless of how much memory we have. Its only the LAW
setup that limits what is visible to the system.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'cpu/mpc8xxx/ddr/ddr1_dimm_params.c')
| -rw-r--r-- | cpu/mpc8xxx/ddr/ddr1_dimm_params.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/cpu/mpc8xxx/ddr/ddr1_dimm_params.c b/cpu/mpc8xxx/ddr/ddr1_dimm_params.c index 2e0a209b4f..9184764418 100644 --- a/cpu/mpc8xxx/ddr/ddr1_dimm_params.c +++ b/cpu/mpc8xxx/ddr/ddr1_dimm_params.c @@ -33,10 +33,10 @@ * 2 or 5 bits off and shifting them up to the top. */ -static phys_size_t +static unsigned long long compute_ranksize(unsigned int mem_type, unsigned char row_dens) { - phys_size_t bsize; + unsigned long long bsize; /* Bottom 2 bits up to the top. */ bsize = ((row_dens >> 2) | ((row_dens & 3) << 6)); |