ppc/8xxx: Refactor code to determine if PCI is enabled & agent/host

Refactor the code into a simple bitmask lookup table that determines if
a given PCI controller is enabled and if its in host/root-complex or
agent/end-point mode.

Each processor in the PQ3/MPC86xx family specified different encodings
for the cfg_host_agt[] and cfg_IO_ports[] boot strapping signals.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

2 files changed, 226 insertions, 0 deletions

diff --git a/cpu/mpc8xxx/Makefile b/cpu/mpc8xxx/Makefile
index 430a75f6f8..5cb6814403 100644
--- a/cpu/mpc8xxx/Makefile
+++ b/cpu/mpc8xxx/Makefile
@@ -11,6 +11,7 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib8xxx.a
 
 COBJS-y	+= cpu.o
+COBJS-$(CONFIG_PCI)	+= pci_cfg.o
 
 SRCS	:= $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
diff --git a/cpu/mpc8xxx/pci_cfg.c b/cpu/mpc8xxx/pci_cfg.c
new file mode 100644
index 0000000000..9c7d92c4d9
--- /dev/null
+++ b/cpu/mpc8xxx/pci_cfg.c
@@ -0,0 +1,225 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <pci.h>
+
+struct pci_info {
+	u16	agent;
+	u16	cfg;
+};
+
+/* The agent field is a bit mask in which each bit represents the value of
+ * cfg_host_agt[] signal and the bit is set of the given interface would be
+ * in agent/end-point mode for the given interface.
+ *
+ * The same idea is true of the cfg field.  The bit will be set if the
+ * interface would be enabled based on the value of cfg_IO_ports[] signal
+ *
+ * On MPC86xx/PQ3 based systems:
+ *   we extract cfg_host_agt from GUTS register PORBMSR
+ *   we extract cfg_IO_ports from GUTS register PORDEVSR
+ *
+ * cfg_IO_ports only exist on systems w/PCIe (we set cfg 0 for systems
+ * without PCIe)
+ */
+
+#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8560)
+static struct pci_info pci_config_info[] =
+{
+	[LAW_TRGT_IF_PCI] = {
+		.agent = (1 << 0) | (1 << 2),
+		.cfg =   0,
+	},
+};
+#elif defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
+static struct pci_info pci_config_info[] =
+{
+	[LAW_TRGT_IF_PCI] = {
+		.agent = (1 << 0),
+		.cfg =   0,
+	},
+};
+#elif defined(CONFIG_MPC8536)
+static struct pci_info pci_config_info[] =
+{
+	[LAW_TRGT_IF_PCI] = {
+		.agent = (1 << 6),
+		.cfg =   0,
+	},
+	[LAW_TRGT_IF_PCIE_1] = {
+		.agent = (1 << 5),
+		.cfg =   (1 << 2) | (1 << 3) | (1 << 5) | (1 << 7),
+	},
+	[LAW_TRGT_IF_PCIE_2] = {
+		.agent = (1 << 3),
+		.cfg =   (1 << 5) | (1 << 7),
+	},
+	[LAW_TRGT_IF_PCIE_3] = {
+		.agent = (1 << 1),
+		.cfg =   (1 << 7),
+	},
+};
+#elif defined(CONFIG_MPC8544)
+static struct pci_info pci_config_info[] =
+{
+	[LAW_TRGT_IF_PCI] = {
+		.agent = (1 << 6),
+		.cfg =   0,
+	},
+	[LAW_TRGT_IF_PCIE_1] = {
+		.agent = (1 << 5),
+		.cfg =   (1 << 2) | (1 << 3) | (1 << 4) | (1 << 5) |
+			 (1 << 6) | (1 << 7),
+	},
+	[LAW_TRGT_IF_PCIE_2] = {
+		.agent = (1 << 3),
+		.cfg =   (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7),
+	},
+	[LAW_TRGT_IF_PCIE_3] = {
+		.agent = (1 << 1),
+		.cfg =   (1 << 6) | (1 << 7),
+	},
+};
+#elif defined(CONFIG_MPC8548)
+static struct pci_info pci_config_info[] =
+{
+	[LAW_TRGT_IF_PCI_1] = {
+		.agent = (1 << 4) | (1 << 6),
+		.cfg =   0,
+	},
+	[LAW_TRGT_IF_PCI_2] = {
+		.agent = (1 << 4) | (1 << 6),
+		.cfg =   0,
+	},
+	/* PCI_2 is always host and we dont use iosel to determine enable/disable */
+	[LAW_TRGT_IF_PCIE_1] = {
+		.agent = (1 << 0) | (1 << 2),
+		.cfg =   (1 << 3) | (1 << 4) | (1 << 7),
+	},
+};
+#elif defined(CONFIG_MPC8568)
+static struct pci_info pci_config_info[] =
+{
+	[LAW_TRGT_IF_PCI] = {
+		.agent = (1 << 0) | (1 << 4) | (1 << 6),
+		.cfg =   0,
+	},
+	[LAW_TRGT_IF_PCIE_1] = {
+		.agent = (1 << 0) | (1 << 2) | (1 << 4),
+		.cfg =   (1 << 3) | (1 << 4) | (1 << 7),
+	},
+};
+#elif defined(CONFIG_MPC8569)
+static struct pci_info pci_config_info[] =
+{
+	[LAW_TRGT_IF_PCIE_1] = {
+		.agent = (1 << 0) | (1 << 6),
+		.cfg =   (1 << 0) | (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7) |
+			 (1 << 8) | (1 << 0xc) | (1 << 0xf),
+	},
+};
+#elif defined(CONFIG_MPC8572)
+static struct pci_info pci_config_info[] =
+{
+	[LAW_TRGT_IF_PCIE_1] = {
+		.agent = (1 << 0) | (1 << 1) | (1 << 4) | (1 << 5),
+		.cfg =   (1 << 2) | (1 << 3) | (1 << 7) |
+			 (1 << 0xb) | (1 << 0xc) | (1 << 0xf),
+	},
+	[LAW_TRGT_IF_PCIE_2] = {
+		.agent = (1 << 0) | (1 << 2) | (1 << 4) | (1 << 6),
+		.cfg =   (1 << 3) | (1 << 7),
+	},
+	[LAW_TRGT_IF_PCIE_3] = {
+		.agent = (1 << 0) | (1 << 3) | (1 << 5) | (1 << 6),
+		.cfg =   (1 << 7),
+	},
+};
+#elif defined(CONFIG_MPC8610)
+static struct pci_info pci_config_info[] =
+{
+	[LAW_TRGT_IF_PCI_1] = {
+		.agent = (1 << 4) | (1 << 5) | (1 << 6),
+		.cfg =   0,
+	},
+	[LAW_TRGT_IF_PCIE_1] = {
+		.agent = (1 << 0) | (1 << 2) | (1 << 5),
+		.cfg =   (1 << 1) | (1 << 4),
+	},
+	[LAW_TRGT_IF_PCIE_2] = {
+		.agent = (1 << 0) | (1 << 1) | (1 << 4),
+		.cfg =   (1 << 0) | (1 << 4),
+	},
+};
+#elif defined(CONFIG_MPC8641)
+static struct pci_info pci_config_info[] =
+{
+	[LAW_TRGT_IF_PCIE_1] = {
+		.agent = 0, /* we dont use agent on 8641 */
+		.cfg =   (1 << 2) | (1 << 3) | (1 << 5) | (1 << 6) |
+			 (1 << 7) | (1 << 0xe) | (1 << 0xf),
+	},
+};
+#elif defined(CONFIG_P1011) || defined(CONFIG_P1020)
+static struct pci_info pci_config_info[] =
+{
+	[LAW_TRGT_IF_PCIE_1] = {
+		.agent = (1 << 0) | (1 << 1),
+		.cfg =   (1 << 0) | (1 << 6) | (1 << 0xe) | (1 << 0xf),
+	},
+	[LAW_TRGT_IF_PCIE_2] = {
+		.agent = (1 << 0) | (1 << 2),
+		.cfg =   (1 << 0xe),
+	},
+};
+#elif defined(CONFIG_P2010) || defined(CONFIG_P2020)
+static struct pci_info pci_config_info[] =
+{
+	[LAW_TRGT_IF_PCIE_1] = {
+		.agent = (1 << 0) | (1 << 1) | (1 << 4) | (1 << 5),
+		.cfg =   (1 << 0) | (1 << 2) | (1 << 4) | (1 << 6) |
+			 (1 << 0xd) | (1 << 0xe) | (1 << 0xf),
+	},
+	[LAW_TRGT_IF_PCIE_2] = {
+		.agent = (1 << 0) | (1 << 2) | (1 << 4) | (1 << 6),
+		.cfg =   (1 << 2) | (1 << 0xe),
+	},
+	[LAW_TRGT_IF_PCIE_3] = {
+		.agent = (1 << 0) | (1 << 3) | (1 << 5) | (1 << 6),
+		.cfg =   (1 << 2) | (1 << 4),
+	},
+};
+#else
+#error Need to define pci_config_info for processor
+#endif
+
+int is_fsl_pci_agent(enum law_trgt_if trgt, u32 host_agent)
+{
+	return ((1 << host_agent) & pci_config_info[trgt].agent);
+}
+
+int is_fsl_pci_cfg(enum law_trgt_if trgt, u32 io_sel)
+{
+	return ((1 << io_sel) & pci_config_info[trgt].cfg);
+}