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| author | Wolfgang Denk <wd@denx.de> | 2008-02-15 00:22:49 +0100 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2008-02-15 00:22:49 +0100 |
| commit | a4d60bb917ed3d9b47ec8e55348e9bce004fa9b4 (patch) | |
| tree | 842b477a86e2b8a7ce216ef486ec0080b0f48e70 /cpu/ppc4xx/denali_spd_ddr2.c | |
| parent | e4992f12523766360628e196f706d29d49b14bf7 (diff) | |
| parent | 32c70d3420739930165271d9a1b04572adf799fd (diff) | |
Merge ../custodians
Diffstat (limited to 'cpu/ppc4xx/denali_spd_ddr2.c')
| -rw-r--r-- | cpu/ppc4xx/denali_spd_ddr2.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/cpu/ppc4xx/denali_spd_ddr2.c b/cpu/ppc4xx/denali_spd_ddr2.c index 825bc2139c..60f89c97fc 100644 --- a/cpu/ppc4xx/denali_spd_ddr2.c +++ b/cpu/ppc4xx/denali_spd_ddr2.c @@ -3,7 +3,7 @@ * This SPD SDRAM detection code supports AMCC PPC44x CPUs with a Denali-core * DDR2 controller, specifically the 440EPx/GRx. * - * (C) Copyright 2007 + * (C) Copyright 2007-2008 * Larry Johnson, lrj@acm.org. * * Based primarily on cpu/ppc4xx/4xx_spd_ddr2.c, which is... @@ -77,10 +77,10 @@ * memory. * * If at some time this restriction doesn't apply anymore, just define - * CFG_ENABLE_SDRAM_CACHE in the board config file and this code should setup + * CONFIG_4xx_DCACHE in the board config file and this code should setup * everything correctly. */ -#if defined(CFG_ENABLE_SDRAM_CACHE) +#if defined(CONFIG_4xx_DCACHE) #define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */ #else #define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */ |