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| author | roy zang <tie-fei.zang@freescale.com> | 2006-12-04 23:57:35 +0800 |
|---|---|---|
| committer | Zang Tiefei <roy@bus.ap.freescale.net> | 2006-12-04 23:57:35 +0800 |
| commit | d3bb5ec198edad4869ac5276a5899881b7bf5433 (patch) | |
| tree | 409a70e937d5f826df7929d11cb08a7cd207f5cd /cpu/ppc4xx/start.S | |
| parent | 41862d13a87ec58c21166b10fcb754c963bc46f2 (diff) | |
| parent | 9d27b3a0685ff99fc477983f315c04d49f657a8a (diff) | |
Merge /home/roy/CVS/7448/Open_Source/u-boot.git.dev
Diffstat (limited to 'cpu/ppc4xx/start.S')
| -rw-r--r-- | cpu/ppc4xx/start.S | 23 |
1 files changed, 12 insertions, 11 deletions
diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 3fe13daaf3..8e000d3092 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -204,6 +204,18 @@ _start_440: mfspr r1,mcsr mtspr mcsr,r1 #endif + + /*----------------------------------------------------------------*/ + /* CCR0 init */ + /*----------------------------------------------------------------*/ + /* Disable store gathering & broadcast, guarantee inst/data + * cache block touch, force load/store alignment + * (see errata 1.12: 440_33) + */ + lis r1,0x0030 /* store gathering & broadcast disable */ + ori r1,r1,0x6000 /* cache touch */ + mtspr ccr0,r1 + /*----------------------------------------------------------------*/ /* Initialize debug */ /*----------------------------------------------------------------*/ @@ -225,17 +237,6 @@ _start_440: mtspr dbsr,r1 /* Clear all valid bits */ skip_debug_init: - /*----------------------------------------------------------------*/ - /* CCR0 init */ - /*----------------------------------------------------------------*/ - /* Disable store gathering & broadcast, guarantee inst/data - * cache block touch, force load/store alignment - * (see errata 1.12: 440_33) - */ - lis r1,0x0030 /* store gathering & broadcast disable */ - ori r1,r1,0x6000 /* cache touch */ - mtspr ccr0,r1 - #if defined (CONFIG_440SPE) /*----------------------------------------------------------------+ | Initialize Core Configuration Reg1. |