diff options
| author | Stefan Roese <sr@denx.de> | 2008-03-03 17:27:02 +0100 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2008-03-15 07:28:05 +0100 |
| commit | 71665ebf88408ff2acb762af47989fd4365b321a (patch) | |
| tree | 7b728da4cbaf7b5d31d05315cc28ae33fbcbb183 /cpu/ppc4xx | |
| parent | c813f1f835a7edfdb929f2843b09db72cd5cd2f2 (diff) | |
ppc4xx: Add Canyonlands NAND booting support
460EX doesn't support a fixed bootstrap option to boot from 512 byte page
NAND devices. The only bootstrap option for NAND booting is option F for
2k page devices. So to boot from a 512 bype page device, the I2C bootstrap
EEPROM needs to be programmed accordingly.
This patch adds basic NAND booting support for the AMCC Canyonlands aval
board and also adds support to the "bootstrap" command, to enable NAND
booting I2C setting.
Tested with 512 byte page NAND device (32MByte) on Canyonlands.
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'cpu/ppc4xx')
| -rw-r--r-- | cpu/ppc4xx/start.S | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index cdfc9436b0..8d2777dcd9 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -403,7 +403,8 @@ rsttlb: tlbwe r0,r1,0x0000 /* Invalidate all entries (V=0)*/ 2: #if defined(CONFIG_NAND_SPL) -#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) /* * Enable internal SRAM (only on 440EPx/GRx, 440EP/GR have no OCM) */ @@ -415,6 +416,11 @@ rsttlb: tlbwe r0,r1,0x0000 /* Invalidate all entries (V=0)*/ mfdcr r1,isram0_pmeg and r1,r1,r2 /* Disable pwr mgmt */ mtdcr isram0_pmeg,r1 +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) + lis r1,0x4000 /* BAS = 8000_0000 */ + ori r1,r1,0x4580 /* 16k */ + mtdcr isram0_sb0cr,r1 +#endif #endif #if defined(CONFIG_440EP) /* |