diff options
| author | Zang Roy-r61911 <tie-fei.zang@freescale.com> | 2006-12-05 16:42:30 +0800 |
|---|---|---|
| committer | Andrew Fleming-AFLEMING <afleming@freescale.com> | 2007-04-23 19:58:27 -0500 |
| commit | 96629cbabdb727d4a5e62542deefc01d498db6dc (patch) | |
| tree | 2986662963b96ae374191aca21231a92b12f6a0c /cpu | |
| parent | 63247a5acd58032e6cf33f525bc3923b467bac88 (diff) | |
u-boot: Fix e500 v2 core reset bug
The following patch fixes the e500 v2 core reset bug.
For e500 v2 core, a new reset control register is added to reset the
processor.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Diffstat (limited to 'cpu')
| -rw-r--r-- | cpu/mpc85xx/cpu.c | 21 |
1 files changed, 15 insertions, 6 deletions
diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 0507c47e6e..2fe4f2abba 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -140,16 +140,25 @@ int checkcpu (void) int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) { + uint pvr; + uint ver; + pvr = get_pvr(); + ver = PVR_VER(pvr); + if (ver & 1){ + /* e500 v2 core has reset control register */ + volatile unsigned int * rstcr; + rstcr = (volatile unsigned int *)(CFG_IMMR + 0xE00B0); + *rstcr = 0x2; /* HRESET_REQ */ + }else{ /* * Initiate hard reset in debug control register DBCR0 * Make sure MSR[DE] = 1 */ - unsigned long val; - - val = mfspr(DBCR0); - val |= 0x70000000; - mtspr(DBCR0,val); - + unsigned long val; + val = mfspr(DBCR0); + val |= 0x70000000; + mtspr(DBCR0,val); + } return 1; } |