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authorSiva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>2017-05-25 14:25:55 +0530
committerMichal Simek <michal.simek@xilinx.com>2018-05-11 09:23:43 +0200
commit9ca8388059de8f10e035fbdcaa418ec3caeb0599 (patch)
tree36e2b08b16920c55baaa66c614b61faa0b6cdf4e /doc/README.at91
parent6de7a5b90701fb306b150d0ed32f7b59b51bbbc5 (diff)
nand: zynq: Add support for 16-bit buswidth
This patch adds support for 16-bit buswidth by determining the bus width based on mio configuration. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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