diff options
| author | Armando Visconti <armando.visconti@st.com> | 2012-03-26 00:09:55 +0000 |
|---|---|---|
| committer | Joe Hershberger <joe.hershberger@ni.com> | 2012-04-04 10:47:09 -0500 |
| commit | aa51005c3f7e517164fa000d68672041f6c4191f (patch) | |
| tree | 83108435981ec813e9f8bcb007237021bd8245f5 /doc/README.phytec.pcm030 | |
| parent | 024333c96fecb698efe703e01f2326c1256114a4 (diff) | |
net/designware: Consecutive writes must have delay
This patch solves a TX/RX problem which happens at 10Mbps, due to the
fact that we are not respecting 4 cyles of the phy_clk (2.5MHz) between
two consecutive writes on the same register.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Diffstat (limited to 'doc/README.phytec.pcm030')
0 files changed, 0 insertions, 0 deletions