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authorPeter Tyser <ptyser@xes-inc.com>2008-10-27 16:42:00 -0500
committerAndrew Fleming-AFLEMING <afleming@freescale.com>2008-10-27 16:45:43 -0500
commit4442f45b0e1cbad35aa22d4cad22b90a57e3f32d (patch)
tree30016ac1c44a431c4356dd17a3de4cd274d1a472 /doc/README.silent
parentcd4251624205cb97104f6e32679dc7754934f711 (diff)
85xx: Update MPC85xx_PORDEVSR_IO_SEL mask
The MPC8572 has a 4-bit wide PORDEVSR IO_SEL field. Other MPC85xx processors have a 3-bit wide IO_SEL field but have the most significant bit is wired to 0 so this change should not affect them. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
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